FM24CL64-S データシートの表示（PDF） - Unspecified

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FM24CL64-S

64Kb Serial 3V FRAM Memory

Unspecified 

FM24CL64

Diagram Notes

All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read

and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional

relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

SCL

tR

tHIGH

` tF

tLOW

tSP

tSP

tSU:SDA

t

BUF

SDA

1/fSCL

t

HD:DAT

t

SU:D AT

Start

Stop Start

t

AA

t

DH

Acknowledge

Write Bus Timing

SCL

SDA

tSU:STO

t

HD:DAT

tHD:STA

t

SU:DAT

t

AA

Start

Stop Start

Acknowledge

Data Retention (VDD = 2.7V to 3.65V unless otherwise specified)

Parameter

Min

Units

Notes

Data Retention

10

Years

1

Notes

1. Endurance is the guaranteed number of read- or write-cycles per address that can be

performed while maintaining the specified data retention. It is unlikely to reach this

limit for most applications.

Rev 2.0

July 2003

Page 11 of 13

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