FM93C66AV データシートの表示（PDF） - Fairchild Semiconductor

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FM93C66AV

4K-Bit Serial CMOS EEPROM(MICROWIRE™ Synchronous Bus)

Fairchild Semiconductor 

Timing Diagrams (Continued)

WRITE DISABLE CYCLE (WDS)

tCS

CS

SK

DI

1 0 0 An An-1

A1 A0

Start Opcode

Address

Bit Bits(2)

Bits(8/9)

High - Z

DO

93C66A (ORG=1; An=A7):

Address bits pattern -> 0-0-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1)

93C66A (ORG=0; An=A8):

Address bits pattern -> 0-0-x-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1)

WRITE CYCLE (WRITE)

tCS

CS

SK

DI

1 0 1 An An-1

A1 A0 Dn Dn-1

D1 D0

Start Opcode

Address

Data

Bit Bits(2)

Bits(8/9)

Bits(16/8)

High - Z

DO

93C66A (ORG=1; An=A7; Dn=D15):

Address bits pattern -> A7-A6-A5-A4-A3-A2-A1-A0; User defined

Data bits pattern -> D15-to-D0; User defined

93C66A (ORG=0; An=A8; Dn=D7):

Address bits pattern -> A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined

Data bits pattern -> D7-to-D0; User defined

tWP

Ready

Busy

WRITE ALL CYCLE (WRALL)

tCS

CS

SK

DI

1 0 0 An An-1

A1 A0 Dn Dn-1

D1 D0

Start Opcode

Address

Data

Bit Bits(2)

Bits(8/9)

Bits(16/8)

High - Z

DO

93C66A (ORG=1; An=A7; Dn=D15):

Address bits pattern -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Data bits pattern -> D15-to-D0; User defined

93C66A (ORG=0; An=A8; Dn=D7):

Address bits pattern -> 0-1-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Data bits pattern -> D7-to-D0; User defined

tWP

Ready

Busy

FM93C66A Rev. B.1

9

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