FM93C56LZEN データシートの表示（PDF） - Fairchild Semiconductor

部品番号

コンポーネント説明

メーカー

FM93C56LZEN

(MICROWIRE™ Bus Interface) 2048-Bit Serial EEPROM with Data Protect and Sequential Read

Fairchild Semiconductor 

Functional Description

A typical Microwire cycle starts by first selecting the device

(bringing the CS signal high). Once the device is selected, a valid

Start bit (“1”) should be issued to properly recognize the cycle.

Following this, the 2-bit opcode of appropriate instruction should

be issued. After the opcode bits, the 8-bit address information

should be issued. For certain instructions, some (or all) of these

8 bits are don’t care values (can be “0” or “1”), but they should still

be issued. Following the address information, depending on the

instruction (WRITE and WRALL), 16-Bit data is issued. Other-

wise, depending on the instruction (READ and PRREAD), the

device starts to drive the output data on the DO line. Other

instructions perform certain control functions and do not deal with

data bits. The Microwire cycle ends when the CS signal is brought

low. However during certain instructions, falling edge of the CS

signal initiates an internal cycle (Programming), and the device

remains busy till the completion of the internal cycle. Each of the

10 instructions is explained in detail in the following sections.

Memory Instructions

Following five instructions, READ, WEN, WRITE, WRALL and

WDS are specific to operations intended for memory array. The

PRE pin should be held low during these instructions.

1) Read and Sequential Read (READ)

READ instruction allows data to be read from a selected location

in the memory array. Input information (Start bit, Opcode and

Address) for this instruction should be issued as listed under

Table1. Upon receiving a valid input information, decoding of the

opcode and the address is made, followed by data transfer from

the selected memory location into a 16-bit serial-out shift register.

This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)

is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit

(logical 0) precedes this 16-bit data output string. Output data

changes are initiated on the rising edge of the SK clock. After

reading the 16-bit data, the CS signal can be brought low to end

the Read cycle. The PRE pin should be held low during this cycle.

Refer Read cycle diagram.

This device also offers “sequential memory read” operation to

allow reading of data from the additional memory locations instead

of just one location. It is started in the same manner as normal read

but the cycle is continued to read further data (instead of terminat-

ing after reading the first 16-bit data). After providing 16-bit data,

the device automatically increments the address pointer to the

next location and continues to provide the data from that location.

Any number of locations can be read out in this manner, however,

after reading out from the last location, the address pointer points

back to the first location. If the cycle is continued further, data will

be read from this first location onward. In this mode of read, the

dummy-bit is present only when the very first data is read (like

normal read cycle) and is not present on subsequent data reads.

The PRE pin should be held low during this cycle. Refer Sequen-

tial Read cycle diagram.

2) Write Enable (WEN)

When VCC is applied to the part, it “powers up” in the Write Disable

(WDS) state. Therefore, all programming operations (for both

memory array and Protect Register) must be preceded by a Write

Enable (WEN) instruction. Once a Write Enable instruction is

executed, programming remains enabled until a Write Disable

(WDS) instruction is executed or VCC is completely removed from

the part. Input information (Start bit, Opcode and Address) for this

WEN instruction should be issued as listed under Table1. The

device becomes write-enabled at the end of this cycle when the

CS signal is brought low. The PRE pin should be held low during

this cycle. Execution of a READ instruction is independent of WEN

instruction. Refer Write Enable cycle diagram.

3) Write (WRITE)

WRITE instruction allows write operation to a specified location in

the memory with a specified data. This instruction is valid only

when the following are true:

I Device is write-enabled (Refer WEN instruction)

I Address of the write location is not write-protected

I PE pin is held high during this cycle

I PRE pin should be held low during this cycle

Input information (Start bit, Opcode, Address and Data) for this

WRITE instruction should be issued as listed under Table1. After

inputting the last bit of data (D0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes tWP time

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

The status of the internal programming cycle can be polled at any

time by bringing the CS signal high again, after tCS interval. When

CS signal is high, the DO pin indicates the READY/BUSY status

of the chip. DO = logical 0 indicates that the programming is still

in progress. DO = logical 1 indicates that the programming is

finished and the device is ready for another instruction. It is not

required to provide the SK clock during this status polling. While

the device is busy, it is recommended that no new instruction be

issued. Refer Write cycle diagram.

It is also recommended to follow this instruction (after the device

becomes READY) with a Write Disable (WDS) instruction to

safeguard data against corruption due to spurious noise, inadvert-

ent writes etc.

4) Write All (WRALL)

Write all (WRALL) instruction is similar to the Write instruction

except that WRALL instruction will simultaneously program all

memory locations with the data pattern specified in the instruction.

This instruction is valid only when the following are true:

I Protect Register has been cleared (Refer PRCLEAR

instruction)

I Device is write-enabled (Refer WEN instruction)

I PE pin is held high during this cycle

I PRE pin should be held low during this cycle

Input information (Start bit, Opcode, Address and Data) for this

WRALL instruction should be issued as listed under Table1. After

inputting the last bit of data (D0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes tWP time

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Status of the internal programming can be polled as described

under WRITE instruction description. While the device is busy, it

is recommended that no new instruction be issued. Refer Write All

cycle diagram.

FM93CS56 Rev. C.1

6

www.fairchildsemi.com

Share Link: