SK100E131PJ データシートの表示（PDF） - Semtech Corporation
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SK100E131PJ Datasheet PDF : 4 Pages
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HIGH-PER.ORMANCE PRODUCTS
Description
Features
SK10/100E131
4-Bit D .lip-.lop
The SK10/100E131 is a Quad master-slave D-type • 1100 MHz Minimum Toggle Frequency
flip-flop with differential outputs. Each flip-flop may • Differential Outputs
be clocked separately by holding Common Clock (CC) • Individual and Common Clocks
LOW and using the Clock Enable (CE*) inputs for • Individual Resets (asynchronous)
clocking. Common clocking is achieved by holding • Paired Sets (asynchronous)
the CE inputs LOW and using CC to clock all four flip- • Extended 100E VEE Range of –4.2V to –5.5V
flops. In this case, the CE* inputs perform the function • Internal 75KΩ Input Pulldown Resistors
of controlling the common clock to each flip-flop.
• Fully Compatible with MC10/100E131
• Specified Over Industrial Temperature Range:
Individual asynchronous resets are provided (R).
–40oC to +85oC
Asynchronous set controls (S) are ganged together in • ESD Protection of >4000V
pairs, with the pairing chosen to reflect physical chip • Available in 28-pin PLCC Package
symmetry.
Data enters the master when both CC and CE* are LOW,
and transfers to the slave when either CC or CE (or both)
go HIGH.
Pin Description
Pin Names
Functional Block Diagram
D3
CE3*
R3
S
DQ
Q
R
Q3
Q3*
Pin
D0 - D3
CE0* - CE3*
R0 - R3
CC
S03, S12
Q0 - Q3
Q0* - Q3*
Function
Data Inputs
Clock Enables (individual)
Resets
Common Clock
Sets (paired)
True Outputs
Inverting Outputs
D2
CE2*
R2
S03
S12
CC
R1
CE1*
D1
R0
CE0*
D0
D
S
Q
Q
R
Q2
Q2*
R
Q
Q1*
D
S
Q
Q1
R
Q
Q0*
DQ
Q0
S
Pinout
25 24 23 22 21 20 19
CE3* 26
18 Q2*
D3 27
17 Q2
S12 28
VEE 1
CC 2
28 Lead PLCC
(Top View)
16 VCC
15 Q1*
14 Q1
S03 3
13 Q0*
D0 4
12 Q0
5
67
8
9 10 11
Revision 2/ March 27, 2002
1
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