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LC5739 データシートの表示(PDF) - SANYO -> Panasonic

部品番号
コンポーネント説明
メーカー
LC5739
SANYO
SANYO -> Panasonic SANYO
LC5739 Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC5739 Terminal Description
LC5739
Pin Name
VSS
VDD1
VDD2
BAK
CUP1,2
S port
S1 - S4
P1 port
P10 - P13
P0 port
P00 - P03
LIGHT
ALM1
SEG1
- SEG32
COM1
- COM4
No.
2
62
61
1
31, 32
36
35
4
3
5
6
7
8
9
10
11
12
59
60
42-57
14-29
30
41
58
13
I/O
Function description
Option
- Power terminal (-)
- •Power terminal(+) (Ag battery version)
Battery version
•Voltage supply to LCD driver (Li battery version, EXTV
Ag/Li/EXTV
version) (C is connected between VDD1 and VSS.)
•Voltage supply to logic unit (Ag battery version,
Back up flag off at Li battery version.)
- •Power terminal(+) (Li battery version, EXTV version)
Battery version
•Voltage supply to LCD driver (Ag battery version)
Ag/Li/EXTV
(C is connected between VDD2 and VSS.)
•Voltage supply to logic unit (EXTV version, Back up flag
is ON at Li battery version.)
- •Power terminal(+)
•For Li battery version, a capacitor must be connected
across BAK and VSS to prevent logic unit from
malfunctioning.
- Capacitor connecting terminals for step-up
(doubler/tripler)
I •4-bit input port
•LSI reset by S1-S4
•Input for HALT release
Enable/Disable
•LSI system is reset by applying VDD to S1 to S4
simultaneously (Mask option).
•Programmable pull-down resistor
•”L”-level hold Tr.
•”L”-level hold Tr.
Provided/Not provided
I/O •4-bit input/output port
•”L”-level hold Tr.
•CMOS output
Provided/Not provided
•Input for HALT release
•Programmable pull-down resistor
•”L”-level hold Tr.
•”H”-level hold Tr.
Provided/Not provided
•”H”-level hold Tr.
I/O •4-bit input/output port
”H”-level hold Tr.
•CMOS output
Provided/Not provided
•”H”-level hold Tr.
O Output port
O •Output port
•Output terminal to deliver melody signal or buzzer with
SAS or TMEL instruction.
(Buzzer : 4kHz/2kHz/1kHz modulation signal or non
modulation signal.)*
(Melody signal : 3 octaves)
O LCD output terminals for segment
O LCD output terminals for common
•Output form
segment/CMOS
•Segment data
SP=0 - FH
DBUS=a/b/c/d/e/f/g/h
LCD duty
1/1,1/2,1/3,1/4
Continue.
No.6704-8/18

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