SK100E445PJ データシートの表示（PDF） - Semtech Corporation

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SK100E445PJ

4-Bit Serial/Parallel Converter

Semtech Corporation 

SK10/100E445

HIGH-PER.ORMANCE PRODUCTS

Application Information (continued)

Perhaps the easiest way to delay the second clock relative

to the first is to take advantage of the differential clock

inputs on the E445. By connecting the clock for the

second E445 to the complimentary clock input pin, the

device will clock a half a clock period after the first E445

(Figure 4). Utilizing this simple technique will raise

the potential conversion frequency up to 1.4 GHz. The

divide by eight clock of the second E445 should be

used to synchronize the parallel data to the rest of the

system as the parallel data of the two E445’s will no

longer by synchronized. This skew problem between

the outputs can be worked around as the parallel

information will be static for eight more clock pulses.

CLOCK

CLOCK*

SERIAL

INPUT

DATA

E445a

SIN

SIN*

SOUT

SOUT*

Q3 Q2 Q1 Q0

Q7 Q6 Q5 Q4

PARALLEL OUTPUT DATA

E445b

SIN

SIN*

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

CLOCK A

CLOCK B

Tpd CLK

to SOUT

800 ps

1150 ps

Figure 4. Extended Frequency 1:8 Demultiplexer

100 ps

CLK

SINA

Q0

Q1

Q2

Q3

Q4 (Q0 a)

Q5 (Q1 a)

Q6 (Q2 a)

Q7 (Q3 a)

SOUTb

SOUTa

CL/4a

CL/4b

CL/8a

CL/8b

Revision 2/April 10, 2002

Dn - 4 Dn - 3 Dn - 2 Dn - 1 Dn

Dn+1 Dn+2 Dn+3

Dn–4

Dn–3

Dn–2

Dn–1

Dn

Dn+1

Dn+2

Dn+3

Dn - 4 Dn - 3 Dn - 2 Dn - 1

Dn

Dn+1 Dn+2 Dn+3

Dn - 4 Dn - 3 Dn - 2 Dn - 1 Dn

Dn+1

Figure 5. Timing Diagram A: 1:8 Serial to Parallel Conversion

8

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