FSA1258(2008) データシートの表示（PDF） - Fairchild Semiconductor

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FSA1258
(Rev.:2008)

Low-RON Low-Voltage, Dual SPST Analog Switch with Low-ICCT “A” Option

Fairchild Semiconductor 

Test Diagrams (Continued)

VSW

GND

B0nB1

VIN

GND

RS

tRISE = 2.5ns

nA

CL

VOUT

RL

GND

VCC

Input- VSel

0V 10%

90%

VCC/2

VOUT

0.9 •VOUT

tBBM

0.9 • VOUT

VSel

GND

RL and CL are functions of the application

environment (50Ω, 75Ω, or 100Ω).

CL includes test fixture and stray capacitance.

Figure 9. Break-Before-Make Interval Timing

GND

VS

GND

GND

RS and RT are functions of the application

environment (50, 75, or 100 ).

Network Analyzer

RS

V IN

VS

GND

RT

GND

V OUT

Figure 10. Bandwidth

Network Analyzer

RS

RT

GND

VS

V Sel

GND

GND

GND

GND

V OUT

RT

RS and RT are functions of the application

GND

environment (50, 75, or 100 ).

Off Isolation= 20 Log (VOUT / VIN)

Figure 11. Channel Off Isolation

© 2004 Fairchild Semiconductor Corporation

FSA1256(A) / FSA1257(A) / FSA1258(A) Rev. 1.0.5

7

www.fairchildsemi.com

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