FSEZ13X7 データシートの表示（PDF） - Fairchild Semiconductor

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FSEZ13X7

Design Guideline for Primary Side Regulated (PSR) Flyback Converter Using FAN103 and FSEZ13X7

Fairchild Semiconductor 

AN-8033

[STEP-7] Determine the Output Filter Stage

The peak to peak ripple of capacitor current is given as:

ΔICAP

=

NP

NS

I PK

DS

(39)

The voltage ripple on the output is given by:

ΔVO

=

ΔIC ⋅TD

2CO

⋅ ( ΔIC − IO N

ΔIC

)2

+ ΔIC

⋅ RC

(40)

Sometimes it is impossible to meet the ripple specification

with a single output capacitor due to the high ESR of the

electrolytic capacitor. Then, additional LC filter stages

(post filter) can be used. When using the post filters, be

careful not to place the corner frequency too low. Too low

a corner frequency may make the system unstable or limit

the control bandwidth. It is typical to set the corner

frequency of the post filter at around 1/10~1/5 of the

switching frequency.

(Design Example) Assuming 470µF electrolytic

capacitor with 30mΩ ESR for output capacitor, the

voltage ripple on the output is:

ΔVO

=

ΔIC ⋅TD

2CO

⋅ ( ΔIC − ION

ΔIC

)2

+

ΔIC

⋅ RC

= 137mV

[STEP-8] Cable Voltage Drop Compensation

When it comes to cellular phone charger application, the

actual battery is located at the end of cable, which causes

typically several percentage of voltage drop on the actual

battery voltage. FAN103 and FSEZ13X7 have cable

voltage drop compensation that can be programmed by a

resistor on the COMR pin, as shown in Table 3. The

resistances of the standard 1.8m cable for different AWG

are summarized in Table 4.

Table 3. Cable Compensation

Percentage of Voltage Drop

Compensation

7%

6%

5%

4%

3%

2%

1%

0%

COMR Resistor

Infinite (Open)

900kΩ

380kΩ

230kΩ

380kΩ

145kΩ

100kΩ

45kΩ

(Design

Example)

Assuming

26AWG/1.8m cable is used, the voltage

drop at maximum output current is:

ΔVO = RCABLE ⋅ IO = 0.48 ⋅ 0.75 = 0.36V

ΔVO = 0.36 = 7.2%

VO

5

The default setting can be used without

any resistor on COMR pin. To improve

the noise immunity of COMR pin, it is

typical to connect a 1µF bypass capacitor

on the COMR pin.

[STEP-9] Design RCD Snubber in Primary

Side

When the power MOSFET is turned off, there is a high-

voltage spike on the drain due to the transformer leakage

inductance. This excessive voltage on the MOSFET may

lead to an avalanche breakdown and eventually failure of

the device. Therefore, it is necessary to use an additional

network to clamp the voltage. The RCD snubber circuit

and MOSFET drain voltage waveform are shown in Figure

14. The RCD snubber network absorbs the current in the

leakage inductance by turning on the snubber diode (Dsn)

once the MOSFET drain voltage exceeds the voltage of

node X as depicted in Figure 14. In the analysis of snubber

network, it is assumed that the snubber capacitor is large

enough that its voltage does not change significantly during

one switching cycle. The snubber capacitor should be

ceramic or a material that offers low ESR. Electrolytic or

tantalum capacitors are unacceptable due to these reasons.

Np: Ns

ID

Io

D

+

VDL

-

VSN

Csn1

Lm

+

Rsn1

- VD +

+

L

VO

O

A

D

-

X

-

Dsn

Llk

Ids

+

Vds

Vgs

-

Idspk

Ids

15~20% of BVdss

Table 4. Resistance of 1.8M Cable for Different AWG

AWG

24

25

26

Ω/m

0.084

0.106

0.134

Resistance for 1.8m

Cable

0.30Ω

0.38Ω

0.48Ω

© 2009 Fairchild Semiconductor Corporation

Rev. 1.0.1 • 5/6/10

10

VOS

Vsn

NP

NS

(VO

+ VF

)

BVdss

VDL

Vds

Figure 14. Snubber Circuit and its Waveforms

www.fairchildsemi.com

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