FSEZ13X7 データシートの表示（PDF） - Fairchild Semiconductor
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FSEZ13X7
Fairchild Semiconductor
FSEZ13X7 Datasheet PDF : 16 Pages
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AN-8033
V min1
DD
=
Na
NS
(Vo
+ VF ) −VFa
(22)
The actual VDD voltage at heavy load is higher than
Equation (8) due to the overshoot by the leakage
inductance, which is proportional to the voltage overshoot
of MOSFET drain-to-source voltage shown in Figure 10.
Considering the effect of voltage overshoot, the VDD
voltages for nominal output voltage and minimum output
voltage are given as:
V max
DD
≅
Na
NS
(VO
+ VF
+
NS
NP
VOS ) −VFa
(23)
V min 2
DD
≅
Na
NS
(VO min
+ VF
+
NS
NP
VOS ) −VFa
(24)
where VFa is the diode forward-voltage drop of auxiliary
winding diode.
Figure 10. VDD and Winding Voltage
(Design Example) Assuming that drain voltage
overshoot is same as the reflected output voltage, the
maximum drain voltage is given as:
V max
DS
= VDLmax
+ VRO
+ VOS
= VDLmax
+ 2VRO
For 700V MOSFET with 25% margin, the reflected
output voltage is obtained as:
VDD min1
=
Na
NS
(5 + 0.55) − 0.7
>
5.5 + 3
∴ Na > 1.66
NS
V max
DD
=
Na
NS
(5 + 0.55 + 1 72) − 0.7
13
<
24
∴ Na < 2.23
NS
V min 2
DD
=
Na
NS
(1.25 + 0.55 + 1 72) − 0.7
13
>
5.5
∴ Na > 0.84
NS
To minimize the power consumption of PWM IC, it is
required to keep VDD as low as possible. Therefore,
Na/Ns is determined as 1.66.
[STEP-4] Design the Transformer
Figure 11 shows the definition of MOSFET conduction
time (tON), diode conduction time (tD) and non-conduction
time (tOFF). The sum of MOSFET conduction time and
diode conduction time at 70% of nominal output voltage is
obtained as:
TON
+ TD
= TON (1+
NS
NP
⋅
V min
DL@ B
0.7 ⋅VO + VF
)
(25)
The first step to design the transformer is to determine how
much non-conduction time (tOFF) is allowed in DCM
operation.
Once the tOFF is determined by considering the frequency
variation caused by frequency hopping and its own
tolerance, the MOSFET conduction time is obtained as:
TON @ B
=
(1 +
1/ fS − TOFF
NS
NP
⋅
V min
DL @ B
0.7 ⋅VON +VF
)
(26)
V max
DS
=
0.75× 700
>
373 +
2VRO
∴VRO < 76V
Setting VRO=72 and VF=0.55, the turns ratio NP/NS is
obtained as:
NP = VRO = 72 = 13
NS (Vo + VF ) 5.55
The allowable VDD range is from 5.5 to 24V,
considering the tolerance. Considering voltage ripple
on VDD caused by burst operation at no load
condition, 3V margin is added for VDD voltage
calculation at no-load condition as:
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 5/6/10
Figure 11. Definition of tON, tD, and tOFF
The transformer primary-side inductance can be calculated
as:
Lm
=
(VDL@ Bmin ⋅ TON @ B )2
2PIN.T @ B
⋅
fS
(27)
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