FSL137H データシートの表示（PDF） - Fairchild Semiconductor

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FSL137H

Green Mode Fairchild Power Switch (FPS™)

Fairchild Semiconductor 

Functional Description

Startup Operation

For startup, the HV pin is connected to the line input or

bulk capacitor through the external resistor, RHV, as

shown in Figure 23. Typical startup current drawn from

the HV pin is 3.5mA and it charges the VDD capacitor

through the resistor RHV. The startup current turns off

when the VDD capacitor voltage reaches VDD-ON. The

VDD capacitor maintains VDD until the auxiliary winding

of the transformer provides the operating current.

Green-Mode Operation

The FSL137H uses feedback voltage (VFB) as an

indicator of the output load and modulates the PWM

frequency, as shown in Figure 25, such that the

switching frequency decreases as load decreases. In

heavy load conditions, the switching frequency is

100kHz. Once VFB decreases below VFB-N (2.5V), the

PWM frequency starts to linearly decrease from 100kHz

to 18kHz to reduce the switching losses. As VFB

decreases below VFB-G (2.4V), the switching frequency

is fixed at 18kHz and FSL137H enters into “deep” green

mode to reduce the standby power consumption. As

VFB decreases below VFB-ZDC (2.1V), FSL137H enters

into burst-mode operation. When VFB drops below VFB-

ZDC, FSL137H stops switching and the output voltage

starts to drop, which causes the feedback voltage to

rise. Once VFB rises above VFB-ZDC, switching resumes.

Burst mode alternately enables and disables switching,

thereby reducing switching loss to improve power

saving, as shown in Figure 26.

Figure 23. Startup Circuit

Slope Compensation

FSL137H is designed for flyback power converters. The

peak-current-mode control is used to optimize system

performance. Slope compensation is added to stabilize

the current loop. FSL137H inserts a synchronized,

positively sloped ramp at each switching cycle.

Soft-Start

The FSL137H has internal soft-start circuit that slowly

increases the SenseFET current after startup. The

typical soft-start time is 5ms during which the VLimit level

is increased in six steps to smoothly establish the

required output voltage, as shown in Figure 24. It also

helps to prevent transformer saturation and reduce the

stress on the secondary diode during startup.

Figure 25. PWM Frequency

Figure 24. Soft-Start Function

Figure 26. Burst Mode Operation

© 2009 Fairchild Semiconductor Corporation

FSL137H Rev. 1.0.3

10

www.fairchildsemi.com

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