SN74LS569AN データシートの表示（PDF） - Motorola => Freescale
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SN74LS569AN Datasheet PDF : 8 Pages
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SN54 / 74LS569A
FUNCTION TABLE
INPUTS
OUTPUTS
CP D C B A LOAD CET CEP U/D ACLR SCLR OE RCO CCO YD YC YB YA
↑ XXXX H
L
L
H
H
↑ XXXX H
L
L
L
H
↑ XXXX H
HXX
H
↑ XXXX H
L
H
X
H
H
L A/R A/R
(QT – CP) + 1
Count Up
H
L A/R A/R
(QT – CP) – 1
Count Down
H
L
H
H NC NC NC NC Count Inhibit
H
L A/R H NC NC NC NC Count Inhibit
Ω XXXX X
L
L
H
H
↑ XXXX X
L
H
H
H
↑ XXXX X
HXH
H
XXXX X
L
L
L
H
↑ XXXX X
L
H
L
H
↑ XXXX X
H
X
L
H
H
L
L
H H H H Overflow
H
L
L
H H H H H Overflow
H
L
H
H H H H H Overflow Inhibit
H
L
L
L L L L Underflow
H
L
L
H L L L L Underflow
H
L
H
H
L L L L Underflow Inhibit
↑ LHLH L
XXX
H
↑ XXXX X
HXH
H
XXXX X
L
L
L
H
↑ XXXX X
L
H
L
H
↑ XXXX X
H
X
L
H
X XXXX X
XXH
L
XXXX X
L
L
L
L
X XXXX X
L
H
L
L
X XXXX X
H
X
L
L
X XXXX X
XXX
X
H
L
H
H
L H L H Load Example
L
L
H
H
L L L L Clear (Synchronous)
L
L
L
L L L L Clear (Synchronous)
L
L
L
H L L L L Clear (Synchronous)
L
L
H
H
L L L L Clear (Synchronous)
X
L
H
H
L L L L Asynchronous Clear
X
L
L
L L L L Asynchronous Clear
X
L
L
H L L L L Asynchronous Clear
X
L
H
H
L L L L Asynchronous Clear
X
HX
X
Hi-Z
Output Disabled
(QT — CP) = Output state prior to clock edge
NC = No change
A/R = Assumes required output state;
X = Don’t care
High except during Overflow and Underflow
LOGIC DIAGRAM
*
D
Q
R
CP Q
OE
ACLR
A
*
YA
B
*
YB
C
D
SCLR
LOAD
CEP
CET
CP
U/D
*
*
FAST AND LS TTL DATA
5-574
YC
YD
RCO
CCO
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