992215735011 データシートの表示（PDF） - Philips Electronics
部品番号
コンポーネント説明
メーカー
992215735011 Datasheet PDF : 17 Pages
| |||
Philips Semiconductors
Frame Transfer CCD Image Sensor
Product specification
FTT1010-M
Architecture of the FTT1010-M
The FTT1010-M consists of a shielded storage section and an open
image section. Both sections are electronically the same and have
the same cell structure with the same properties.The only difference
between the two sections is the optical light shield.
The optical centres of all pixels in the image section form a square
grid. The charge is generated and integrated in this section. Output
registers are located below the storage section. The output amplifiers
Y and Z are not used in Frame Transfer mode and should be
connected as not-used amplifiers.
After the integration time the charge collected in the image section
is shifted to the storage section. The charge is read out line by line
through the lower output register.
The left and the right half of each output register can be controlled
independently. This enables either single or multiple read-out.
During vertical transport the C3 gates separate the pixels in the
register. The letters W, X, Y and Z are used to define the four
quadrants of the sensor. The central C3 gates of both registers are
part of the W and Z quadrants of the sensor.
Both upper and lower registers can be used for vertical binning.
Both registers also have a summing gate at each end that can be
used for horizontal binning. Figure 2 shows the detailed internal
structure.
Image diagonal (active video only)
Aspect ratio
Active image width x height
Pixel width x height
Geometric fill factor
Image clock pins
Capacity of each clock phase
Number of active lines
Number of black reference lines
Number of dummy black lines
Total number of lines
Number of active pixels per line
Number of overscan (timing) pixels per line
Number of black reference pixels per line
Total number of pixels per line
IMAGE SECTION
17.38 mm
1:1
12.288 x 12.288 mm2
12x12 µm2
100%
A1, A2, A3, A4
2.5nF per pin
1024
2
4
1030
1024
8 (2x4)
40 (2x20)
1072
Storage width x height
Cell width x height
Storage clock phases
Capacity of each clock phase
Number of cells per line
Number of lines
STORAGE SECTION
12.864 x 12.360 mm2
12x12 µm2
B1, B2, B3, B4
2.5nF per pin
1072
1030
Output buffers (three-stage source follower)
Number of registers
Number of dummy cells per register
Number of register cells per register
Output register horizontal transport clock pins
Capacity of each C-clock phase
Overlap capacity between neighbouring C-clocks
Output register Summing Gates
Capacity of each SG
Reset Gate clock phases
Capacity of each RG
OUTPUT REGISTERS
4 (one on each corner)
2 (one above, one below)
14 (2x7)
1072
C1, C2, C3
60pF per pin
20pF
4 pins (SG)
15pF
4 pins (RG)
15pF
1999 September
3
Share Link: 