HT1647_05 データシートの表示（PDF） - Holtek Semiconductor
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HT1647_05 Datasheet PDF : 17 Pages
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Bias Generator
The HT1647 bias voltage belongs to internal resistor
type. It provides two kinds of bias option named 1/5 bias
and 1/4 bias respectively. It is recommended to select
1/5 bias to fit TN-type, STN-type LCDs and select 1/4
bias to fit ECB-type LCDs. It also provides three kinds of
bias current option by programming to suitably drive an
LCD panel. The three kinds of bias current are large,
VLCD
4V
4V
Bias
1/5
1/4
Large Bias Current
300mA
375mA
HT1647
middle, and small, respectively. Usually, large panel
LCD can be excellently displayed by large bias current.
Relatively, it consumes large current when LCD ON
command is used. Small bias current provides low
power consumption during On condition when the LCD
is normally displayed. The following are the reference
value table.
Middle Bias Current
Small Bias Current
100mA
125mA
40mA
50mA
VDD
V LC D
R
V1
R
V2
R
V3
R
V4
R
VSS
1 /5 b ia s
*V R
*V L C D
VDD
V LC D
R
V1
R
V2
R
V3
R
V4
R
VSS
1 /4 b ia s
*V R
*V L C D
* T h e v o lta g e a p p lie d to V L C D p in m u s t b e lo w e r th a n V D D
* A d ju s t V R to fit L C D d is p la y , a t V D D = 5 V , V L C D = 4 V , V R = 1 5 k W ± 2 0 %
Internal Resistor Type Bias Generator Configurations
Interfacing
Only six lines are required to interface with the HT1647.
The CS line is used to initialize the serial interface circuit
and to terminate the communication between the host
controller and the HT1647. If the CS pin is set to 1, the
data and command issued between the host controller
and the HT1647 are first disabled and then initialized.
Before issuing a mode command or mode switching, a
high level pulse is required to initialize the serial inter-
face of the HT1647. The DB0~DB3 are the 4-bit parallel
data input/output lines. Data to be read or written or
commands to be written have to pass through the
DB0~DB3 lines. The RD line is the READ clock input.
Data in the RAM are clocked out on the falling edge of the
RD signal, and the clocked out data will then appear on
the DB0~DB3 lines. It is recommended that the host
controller read correct data during the interval between
the rising edge and the next falling edge of the RD signal.
The WR line is the WRITE clock input. The data, ad-
dress, and command on the DB0~DB3 lines are all
clocked into the HT1647 on the rising edge of the WR
signal. There is an optional IRQ line to be used as an in-
terface between the host controller and the HT1647.
The IRQ pin can be selected as a timer output or a WDT
overflow flag output by the S/W setting. The host con-
troller can perform the time base or the WDT function by
connecting with the IRQ pin of the HT1647.
Rev. 1.30
11
November 10, 2005
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