33C408RPFE20 データシートの表示（PDF） - MAXWELL TECHNOLOGIES

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33C408RPFE20

4 Megabit (512K x 8-Bit) CMOS SRAM

MAXWELL TECHNOLOGIES 

4 Megabit (512K x 8-Bit) CMOS SRAM

33C408

FIGURE 1. AC TEST LOADTIMING WAVEFORM OF READ CYCLE(1)

FIGURE 2. TIMING WAVEFORM OF READ CYCLE (2)

Read Cycle Notes:

1. WE is high for read cycle.

2. All read cycle timing is referenced form the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not

referenced to VOH or VOL levels.

4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and

from device to device.

5. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100%

tested.

6. Device is continuously selected with CS = VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention condition is necessary dur-

ing read and write cycle.

04.16.02 REV 8

All data sheets are subject to change without notice 7

©2002 Maxwell Technologies

All rights reserved.

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