AZ100E14FN データシートの表示（PDF） - AZ Microtek
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AZ100E14FN Datasheet PDF : 5 Pages
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ARIZONA MICROTEK, INC.
AZ10E142
AZ100E142
ECL/PECL 9-bit Shift Register
FEATURES
• 700 MHz Minimum Shift Frequency
• 9-Bit for Byte-Parity Application
• Asynchronous Master Reset
• Dual Clocks
• Operating Range of 4.2V to 5.46V
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor
MC10E142 & MC100E142
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
PLCC 28
PLCC 28 T&R
PLCC 28
PLCC 28 T&R
PART NO.
AZ10E142FN
AZ10E142FNR2
AZ100E142FN
AZ100E142FNR2
MARKING
AZM10E142
AZM10E142
AZM100E142
AZM100E142
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs
serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data,
while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift
direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of
CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
SEL
D8
D7
D6
D5
VCCO
Q8
25
24
23
22
21
20
19
MR
26
18
Q7
CLK1
27
17
Q6
CLK2
28
VEE
1
S-IN
2
Pinout: 28-lead
PLCC (top view)
16
VCC
15
Q5
14
VCCO
D0
3
13
Q4
D1
4
12
Q3
5
6
7
8
9
10
11
D2
D3
D4
VCCO
Q0
Q1
Q2
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
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