GS880F18BGT-5.5IV データシートの表示（PDF） - Giga Semiconductor

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GS880F18BGT-5.5IV

512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

Giga Semiconductor 

Simplified State Diagram with G

GS880F18/32/36BT-xxxV

X

Deselect

W

R

W

R

X

First Write R

CW

CR

W

First Read X

CW

CR

W

X

R

Burst Write

CR

CW

R

W

Burst Read X

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.00 6/2006

11/21

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2006, GSI Technology

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