GS9000C データシートの表示（PDF） - Gennum -> Semtech
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GS9000C Datasheet PDF : 8 Pages
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GS9000C PIN DESCRIPTIONS
PIN NO. SYMBOL TYPE
DESCRIPTION
15
SWC
Input
Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is
accomplished by an external RC time constant connected to this pin.
16
PCLK
Output Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the clock is
located at the centre of the parallel data window within a given tolerance. See Fig. 7.
17
PD0
Output
Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output from
the serial to parallel convertor representing the least significant bit (LSB).
18
19 - 25
VDD
PD1 - PD7
Outputs
Power Supply. Most positive power supply connection.
Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data outputs from
the serial to parallel convertor representing data bit 1 through data bit 7.
26
VSS
27
PD8
Output
Power Supply. Most negative power supply connection.
Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the serial to
parallel convertor representing data bit 8.
28
PD9
Output
Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from the serial
to parallel convertor representing the most significant bit (MSB).
INPUT / OUTPUT CIRCUITS
VDD
VDD
SSC
REXT
EXTERNAL
COMPONENTS
VDD
Fig. 2 Pin 11 SSC
SDI
SCI
VDD
VDD
SCE
Fig. 3 Pin 14 SCE
VDD
BIAS
SDI
SCI
522 - 49 - 01
Fig. 4 Pins 5 - 8 SDI - SCI
4
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