GS9000C データシートの表示（PDF） - Gennum -> Semtech

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GS9000C

GENLINX™ GS9000C Serial Digital Decoder

Gennum -> Semtech 

VDD

VDD

SWC

REXT

6k8

CEXT

EXTERNAL

COMPONENTS

Fig. 5 Pin 15 SWC

VDD

OUTPUT

GND

Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28

SWF, HSYNC, SSI, SSD, PCLK, PD0-9

SERIAL

CLOCK

(SCI)

tCLKL = tCLKH

50%

PARALLEL

DATA

(PDn)

1/2 T

1/2 T

SERIAL

DATA

(SDI)

PARALLEL

CLOCK

50%

(PCLK)

tSU

tHOLD

tD

Fig. 7 Waveforms

TEST SET-UP & APPLICATION INFORMATION

Figure 8 shows the test set-up for the GS9000C operating

from a VDD supply of +5 volts. The differential pseudo ECL

inputs for DATA and CLOCK (pins 5,6,7 and 8) must be

biased between +3.0 and +4.0 volts. In the circuit shown,

these inputs with the resistor values shown, can be directly

driven from the outputs of the GS9005A Reclocking Receiver.

In other cases, such as true ECL level driver outputs, two

biasing resistors are needed on the DATA and CLOCK inputs

and the signals must be AC coupled.

It is critical that the decoupling capacitors connected to pins

12,13 and 18 be chip types and be located as close as

possible to the device pins.

In order to maintain very short interconnections when

interfacing with the GS9005A Receiver, the critical high

speed inputs such as Serial Data (pins 5 and 6) and Serial

Clock (pins 7 and 8) are located along one side of the device

package.

If the automatic standard select function is not used, the

Standard Select bits (pins 9 and 10) do not need to be

connected, however the control input (pin 11) should be

grounded.

5

522 - 49 - 01

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