GS9000C データシートの表示（PDF） - Gennum -> Semtech
部品番号
コンポーネント説明
メーカー
GS9000C Datasheet PDF : 8 Pages
| |||
VCC
+5V
DVCC
+5V
10µ + 10µ +
VCC
10µ
+
0µ1
0µ1
SSI
VCC
0µ1
VCC
0µ1
GND
DGND
INPUT 75
75
ECL
DATA
INPUT
47p
47p
VCC
0µ1
5
DDI
6
DDI
7 VCC2
8 SDI
9 SDI
10 ƒ/2
11 VEE3
4 3 2 1 28 27 26
GS9005A
25
SDO 24
SDO 23
SCO 22
SCO 21 VCC
SS1 20
SS0 19
CD
22n(1)
5p6
12 13 14 15 16 17 18 VCC
113
(2) 910
10n
1k2
SWF
390
390
100
100
100
100
390
390
VCC
100 3k3 100
DGND
100
DGND
DGND
4 3 2 1 28 27 26
25
100
5
SDI
PD7 24
100
6 SDI
7 SCI
8 SCI
9 SS1
10 SS0
11 SSC
GS9000C
PD6
23
PD5
PD4 22
PD3 21
PD2 20
PD1 19
100
100
100
100
100
DVCC
DVCC 12 13 14 15 16 17 18
0µ1
0µ1
100 100 DGND
DGND
DVCC
INPUT SELECTION
SYNC WARNING FLAG
HSYNC OUTPUT
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
STAR
ROUTED
0µ1
+
6µ8
(2)
6µ8 +
VCC
0µ1
1k2
120
GS9010A
1
P/N
STDT 16
2
OUT
VCC 15
3 IN-
CD 14
4 COMP HSYNC 13
3n3 5 LF
GND 12
6 ƒ/2
OSC 11
7 VCC
8 SWF
DLY 10
FVCAP 9
SWF
(3)
50k
VCC
0.1µ
68k
22n
DGND
VCC
82n
VCC
180n
100k
0µ68 (2)
STANDARD TRUTH TABLE
ƒ/2 P/N
00
01
10
11
STANDARD
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
(1) Typical value for input return loss matching
(2) To reduce board space, the two anti-series 6.8µF capacitors (connected across pins 2 and 3 of the GS9010A)
may be replaced with a 1.0µF non-polarized capacitor provided that
(a) the 0.68µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10nF.
(3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
Fig. 11 Application Circuit - Adjustment Free Multi-standard Serial to Parallel Convertor
GS9000C, GS9005A and GS9010A INTERCONNECTIONS
Figure 11 shows an application of the GS9000C in an
adjustment free, multi-standard serial to parallel convertor.
This circuit uses the GS9010A Automatic Tuning Sub-system
IC and a GS9005A Serial Digital Receiver. The GS9005A may
be replaced with a GS9015A Reclocker IC if cable equalization
is not required.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the incoming
data stream is 4ƒsc NTSC,4ƒsc PAL or component 4:2:2.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
over a set range until the system is correctly locked. An
automatic fine tuning (AFT) loop maintains the VCO control
voltage at its centre point through continuous, long term
adjustments of the VCO centre frequency.
During normal operation, the GS9000C Decoder provides
continuous HSYNC pulses which disable the ramp/oscillator
of the GS9010A. This maintains the correct Receiver/
Reclocker VCO frequency. When an interruption to the incoming
data stream is detected by the Receiver/Reclocker, the
Carrier Detect goes LOW and tri-states the AFT loop in order
to maintain the correct VCO frequency for a period of about
2 seconds. This allows the Receiver/Reclocker to rapidly
relock when the signal is re-established.
7
522 - 49 - 01
Share Link: 