GS9000D データシートの表示（PDF） - Gennum -> Semtech
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GS9000D Datasheet PDF : 9 Pages
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VSS
(MSB)
SWF VSS HSYNC PD9 PD8
VSS
4
3
2
SDI
5
28
27
26
25
PD7
SDI
6
24
PD6
SCI
7
SCI
8
GS9000D
TOP VIEW
23
PD5
22
PD4
SS1
9
21
PD3
SS0
10
20
PD2
SSC
11
19
PD1
12
13
14
15
16
17
18
PIN DESCRIPTIONS
PIN NO.
SYMBOL
1
HSYNC
2
VSS
3
SWF
4
5, 6
7, 8
9,10
11
12
13
14
VSS
SDI/SDI
SCI/SCI
SS1/SS0
SSC
VDD
VDD
SCE
VDD VDD
SCE
SWC PCLK
PD0
VDD
(LSB)
Fig. 1 GS9000D Pin Outs, 28 Pin PLCC Package
TYPE
Output
Output
Inputs
Inputs
Output
Input
Input
DESCRIPTION
Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected.
Power Supply. Most negative power supply connection.
Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the
preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the SWC
input.
Power Supply. Most negative power supply connection.
Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3.0V to 4.05V for
operation up to 270MHz. See AC Electrical Characteristics Table for details.
Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3.0V to 4.05V for
operation up to 270MHz. See AC Electrical Characteristics Table for details.
Standard Select Outputs. CMOS (TTL compatible) outputs is generated by a 2-bit internal
binary counter which stops cycling when a valid TRS is detected by the GS9000D.
Standards Select Control. Analog input used to set a time constant for the standards select
hunt period. An external RC sets the time constant.
Power Supply. Most positive power supply connection.
Power Supply. Most positive power supply connection.
Sync Correction Enable. Active high CMOS input which enables sync correction by not
resetting the GS9000D’s internal parallel timing on the first sync error. If the next incoming
sync is in error, internal parallel timing will be reset. This is to guard against spurious HSYNC
errors. When SCE is low, a valid sync will always reset the GS9000D’s parallel timing generator
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