GS90015BCPJE3 データシートの表示（PDF） - Gennum -> Semtech
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GS90015BCPJE3 Datasheet PDF : 13 Pages
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tD
tD
SERIAL
DATA OUT
(SD0)
SERIAL
CLOCK OUT
(SCK)
50%
50%
Fig.1 Waveforms
D GS9015B Reclocking Receiver - Detailed Device Description
E The GS9015B Reclocking Receiver is a bipolar integrated
D circuit containing circuitry necessary to re-clock and
regenerate the NRZI serial data stream.
N S Packaged in a 28 pin PLCC, the receiver operates from a
E N single five volt supply at data rates to 400 Mb/s. Typical power
consumption is 330 mW. Typical output jitter is ±100 ps
M IG at 270 Mb/s.
Serial Digital signals are applied to digital inputs DDI and DDI
M S (pins 5,6).
O E Phase Locked Loop
The phase comparator itself compares the position of
C D transitions in the incoming signal with the phase of the local
oscillator (VCO). The error-correcting output signals are fed
E to the charge pump in the form of short pulses. The charge
R W pump converts these pulses into a “charge packet” which is
accurately proportional to the system phase error.
E The charge packet is then integrated by the second-order
T N loop filter to produce a control voltage for the VCO.
O During periods when there are no transitions in the signal, the
loop filter voltage is required to hold precisely at its last value
N R so that the VCO does not drift significantly between corrections.
Commutating diodes in the charge pump keep the output
O leakage current extremely low, minimizing VCO frequency
F drift.
VCO Centre Frequency Selection
The centre frequency of the VCO is set by one of four external
current reference resistors (RVCO0-RVCO3) connected to
pins 13,14,15 or 17. These are selected by two logic inputs
SS0 and SS1 (pins 20, 21) through a 2:4 decoder according
to the following truth table.
SS1
SS0
0
0
0
1
1
0
1
1
Resistor Selected
RVCO0 (13)
RVCO1 (14)
RVCO2 (15)
RVCO3 (17)
As an alternative, the GS9010A Automatic Tuning Sub-system
and the GS9000B or GS9000S Decoder may be used in
conjunction with the GS9015B to obtain adjustment free and
automatic standard select operation (see Figure17).
With the VCO operating at twice the clock frequency, a clock
phase which is centred on the eye of the locked signal is used
to latch the incoming data, thus maximising immunity to
jitter-induced errors. The alternate phase is used to latch the
output re-clocked data SDO and SDO (pins 25, 24). The true
and inverse clock signals themselves are available from the
The VCO is implemented using a current-controlled SCO and SCO pins 23 and 22.
multivibrator, designed to deliver good stability, low phase
noise and wide operating frequency capability. The frequency
range is design-limited to ±10% about the oscillator centre
frequency.
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