H5PS1G63JFR データシートの表示（PDF） - Hynix Semiconductor

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H5PS1G63JFR

1Gb DDR2 SDRAM

Hynix Semiconductor 

3.2 DC & AC Logic Input Levels

Release

H5PS1G63JFR Series

3.2.1 Input DC Logic Level

Symbol

VIH(dc)

VIL(dc)

Parameter

dc input logic HIGH

dc input logic LOW

3.2.2 Input AC Logic Level

Min.

VREF + 0.125

- 0.3

Max.

VDDQ + 0.3

VREF - 0.125

Units

V

V

Symbol

VIH (ac)

VIL (ac)

Parameter

ac input logic HIGH

ac input logic LOW

DDR2 400,533

DDR2 667,800

Min.

Max.

Min.

Max.

VREF + 0.250 VDDQ+Vpeak VREF + 0.200 VDDQ+Vpeak

VSSQ-Vpeak VREF - 0.250 VSSQ-Vpeak VREF - 0.200

Units

V

V

Symbol

Parameter

VIH (ac)

VIL (ac)

ac input logic HIGH

ac input logic LOW

DDR2 1066

Min.

VREF + 0.200

Max.

VDDQ+Vpeak

VSSQ-Vpeak

VREF - 0.200

3.2.3 AC Input Test Conditions

Units

V

V

Notes

Notes

Notes

Symbol

VREF

VSWING(MAX)

SLEW

Note:

Condition

Input reference voltage

Input signal maximum peak to peak swing

Input signal minimum slew rate

Value

0.5 * VDDQ

1.0

1.0

Units

V

V

V/ns

Notes

1

1

2, 3

VSWING(MAX)

delta TF

Falling Slew = VREF - VIL(ac) max

delta TF

delta TR

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

Rising Slew = VIH(ac) min - VREF

delta TR

1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising

edges and the range from VREF to VIL(ac) max for falling edges as shown in the figure below.

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions

Rev. 1.7 / Nov. 2011

11

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