HD6432676 データシートの表示（PDF） - Renesas Electronics
部品番号
コンポーネント説明
メーカー
HD6432676 Datasheet PDF : 979 Pages
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Item
10.15.4 Pin
Functions
Page
515
515
10.16.4 Pin
520
Functions
11.1 Features
523
Table 11.1 TPU
Functions
11.3.9 Timer
558
Synchronous Register
(TSYR)
15.3.9 Bit Rate
679
Generator (BRR)
Table 15.2
Relationships
between N Setting in
BRR and Bit Rate B
Revision (See Manual for Details)
• PG3/CS3/RAS3/CAS, PG2/CS2/RAS2/RAS
Description amended
The pin function is switched as shown below according to the
operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits
RMTS2 to RMTS0.
• PG1/CS1, PG0/CS0
Description amended
The pin function is switched as shown below according to the
operating mode, bit EXPE, bit PGnDDR, and bit CSnE.
• PH1/CS5/RAS5/SDRAMφ
Description amended
The pin function is switched as shown below according to the
operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2
to RMTS0, and bit PH1DDR.
Table 11.1 amended
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
DTC
TGR
TGR
TGR
TGR
TGR
TGR
activation compare
compare
compare
compare
compare
compare
match or
match or
match or
match or
match or
match or
input capture input capture input capture input capture input capture input capture
DMAC TGRA_0
TGRA_1
TGRA_2
TGRA_3
TGRA_4
TGRA_5
activation compare
compare
compare
compare
compare
compare
match or
match or
match or
match or
match or
match or
input capture input capture input capture input capture input capture input capture
A/D
TGRA_0
TGRA_1
TGRA_2
TGRA_3
TGRA_4
TGRA_5
converter compare
compare
compare
compare
compare
compare
trigger match or
match or
match or
match or
match or
match or
input capture input capture input capture input capture input capture input capture
PPG
TGRA_0/ TGRA_1/ TGRA_2/ TGRA_3/ —
—
trigger TGRB_0
TGRB_1
TGRB_2
TGRB_3
compare
compare
compare
compare
match or
match or
match or
match or
input capture input capture input capture input capture
Bits 7, 6 initial value amended
(Before) - → (After) All 0
Table 15.2 amended
Mode
Smart Card
Interface Mode
Bit Rate
φ × 106
B=
S × 22n+1 × (N + 1)
Error
{ } φ × 106
Error (%) = B × S × 22n+1 × (N + 1) – 1 × 100
Rev. 3.00 Mar 17, 2006 page ix of l
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