UPD16310GF-3L9 データシートの表示（PDF） - NEC => Renesas Technology
部品番号
コンポーネント説明
メーカー
UPD16310GF-3L9 Datasheet PDF : 14 Pages
| |||
µPD16310
PN CONFIGURATION
PIN No.
27
37
36
30
SYMBOL
PC
BLK
STB
A
35
B
31
CLK
25
R/L
1 - 20
45 - 64
26, 39
21, 44
24, 41
22, 23, 42, 43
28, 29, 32 - 34
38, 40
O1 - O40
VDD1
VDD2
VSS1
VSS2
NC
PIN NAME
Polarity Change Input
Blank Input
Latch Strobe Input
Right Data Input/Output
Left Data Input/Output
Clock Input
Shift Direction Control Input
Driver Outputs
Logic Power Supply
Driver Power Supply
Ground (for Logic)
Ground (for Driver)
No Connect
FUNCTION
All driver outputs’ level are inverted while PC is L.
All driver outputs are H or L while BLK is H.
Latch’s status is data through while STB is L.
R/L = H : A = IN, B = OUT
R/L = L : A = OUT, B = IN
Data of shift-register is shifted while CLK is going
H to L. (Negative edge is active.)
H: Right Shift Mode
A → O1 ··· O40 → B
L: left Shift Mode
B → O40 ··· O1 → A
High voltage output 80 V, 50 mA
5.0 V ± 10 %
10 to 70 V
Connect to the system ground.
Connect to the system ground.
No. 33 pin should be open.
TRUTH TABLE 1 (Shift-Register part)
INPUT
R/L
CLK
H
↓
H
H or L
L
↓
L
H or L
IN/OUT
A
B
IN
OUT
IN
OUT
OUT
IN
OUT
IN
SHIFT-REGISTER
DATA is shifted.
No Change.
DATA is shifted.
No Change.
TRUTH TABLE 2 (Latch, Driver part)
INPUT
A (B)
STB
BLK
PC
DRIVER OUTPUT
X
X
H
H
ALL H
X
X
H
L
ALL L
H
L
L
H
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
X
H
L
H
Latch’s data output
X
H
L
L
Latch’s data output (inverting)
X = H or L, H = High Level, L = Low Level
4
Share Link: 