HD4048412 データシートの表示（PDF） - Renesas Electronics

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HD4048412

4-Bit Single-Chip Microcomputer

Renesas Electronics 

HD404849 Series

256 (n – 1) + 255

BR AAA 256n

AAA NOP

BR AAA 256n + 254

BR BBB 256n + 255

256 (n + 1)

BBB NOP

Figure 94 Branching when the Branch Destination is on a Page Boundary

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–

$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data

are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight high-

order bits (PC13–PC6).

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-

bit immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction

as shown in figure 93. If bit 8 of the ROM data is 1, the lower eight bits of ROM data are written to the

accumulator and the B register. If bit 9 is 1, the lower eight bits of ROM data are written to the R1 and R2

port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register,

and also to the R1 and R2 port output registers at the same time.

The P instruction has no effect on the program counter.

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