HD64336022G データシートの表示（PDF） - Renesas Electronics

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HD64336022G

16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Renesas Electronics 

Contents

Section 1 Overview................................................................................................1

1.1 Features.................................................................................................................................. 1

1.2 Internal Block Diagram.......................................................................................................... 3

1.3 Pin Arrangement .................................................................................................................... 4

1.4 Pin Functions ......................................................................................................................... 6

Section 2 CPU........................................................................................................9

2.1 Address Space and Memory Map ........................................................................................ 10

2.2 Register Configuration......................................................................................................... 12

2.2.1 General Registers.................................................................................................... 13

2.2.2 Program Counter (PC) ............................................................................................ 14

2.2.3 Condition-Code Register (CCR)............................................................................. 14

2.3 Data Formats........................................................................................................................ 16

2.3.1 General Register Data Formats ............................................................................... 16

2.3.2 Memory Data Formats ............................................................................................ 18

2.4 Instruction Set ...................................................................................................................... 19

2.4.1 Table of Instructions Classified by Function .......................................................... 19

2.4.2 Basic Instruction Formats ....................................................................................... 28

2.5 Addressing Modes and Effective Address Calculation........................................................ 30

2.5.1 Addressing Modes .................................................................................................. 30

2.5.2 Effective Address Calculation ................................................................................ 33

2.6 Basic Bus Cycle ................................................................................................................... 35

2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 35

2.6.2 On-Chip Peripheral Modules .................................................................................. 36

2.7 CPU States ........................................................................................................................... 37

2.8 Usage Notes ......................................................................................................................... 38

2.8.1 Notes on Data Access to Empty Areas ................................................................... 38

2.8.2 EEPMOV Instruction.............................................................................................. 38

2.8.3 Bit Manipulation Instruction................................................................................... 38

Section 3 Exception Handling .............................................................................45

3.1 Exception Sources and Vector Address ............................................................................... 45

3.2 Register Descriptions ........................................................................................................... 47

3.2.1 Interrupt Edge Select Register 1 (IEGR1) .............................................................. 47

3.2.2 Interrupt Edge Select Register 2 (IEGR2) .............................................................. 48

3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 49

Rev. 4.00 Sep. 23, 2005 Page ix of xxvi

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