HD74HC109FPEL データシートの表示（PDF） - Renesas Electronics

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HD74HC109FPEL

Dual J-KFlip-Flops (with Preset and Clear)

Renesas Electronics 

HD74HC109

Dual J-K Flip-Flops (with Preset and Clear)

REJ03D0561-0200

(Previous ADE-205-434)

Rev.2.00

Oct 11, 2005

Description

Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to

the clock input and changes state on the positive going transition of the clock pulse. Clear and preset are independent of

the clock and accomplished by a low logic level on the corresponding input.

Features

• High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

HD74HC109P

DILP-16 pin

PRDP0016AE-B

(DP-16FV)

P

HD74HC109FPEL SOP-16 pin (JEITA)

PRSP0016DH-B

(FP-16DAV)

FP

HD74HC109RPEL SOP-16 pin (JEDEC)

PRSP0016DG-A

(FP-16DNV)

RP

Note: Please consult the sales office for the above package availability.

Taping Abbreviation

(Quantity)

—

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Function Table

Inputs

Outputs

Preset

Clear

Clock

J

K

Q

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

X

H*1

H*1

H

H

L

L

L

H

H

H

H

L

Toggle

H

H

L

H

Q0

Q0

H

H

H

H

H

L

H

H

L

X

X

Q0

Q0

Note: 1. Q and Q will remain high as long as preset and clear input are low, but Q and Q are unpredictable if preset

and clear input go high simultaneously.

H : High level

L : Low level

X : Irrelevant

Rev.2.00, Oct 11, 2005 page 1 of 7

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