HD74HC131RPEL データシートの表示（PDF） - Renesas Electronics

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HD74HC131RPEL

3-to-8-line Decoder/Demultiplexer with Edge-Triggered Address Registers

Renesas Electronics 

HD74HC131

3-to-8-line Decoder/Demultiplexer with Edge-Triggered Address

Registers

REJ03D0566-0200

(Previous ADE-205-440)

Rev.2.00

Oct 11, 2005

Description

The HD74HC131 is 3-to-8 linedecoder. It has Address select inputs (A, B, C) and D type register.

Address select data store to D type registers, during the positive going transition of the clock pulse.

Output control (G1, G2) are independent of select input and CLK input, and when G1 is low or G2 = High, all outputs is

high.

Features

• High Speed Operation: tpd (CLK to Y) = 20 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 V to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

HD74HC131P

DILP-16 pin

PRDP0016AE-B

(DP-16FV)

P

HD74HC131FPEL SOP-16 pin (JEITA)

PRSP0016DH-B

(FP-16DAV)

FP

HD74HC131RPEL SOP-16 pin (JEDEC)

PRSP0016DG-A RP

(FP-16DNV)

Note: Please consult the sales office for the above package availability.

Taping Abbreviation

(Quantity)

—

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Rev.2.00, Oct 11, 2005 page 1 of 8

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