HD74HCT245FPEL データシートの表示（PDF） - Renesas Electronics
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HD74HCT245FPEL Datasheet PDF : 7 Pages
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HD74HCT245
Octal Bus Transceivers (with 3-state outputs)
REJ03D0665–0200
(Previous ADE-205-554)
Rev.2.00
Mar 30, 2006
Description
This device has an active low enable input G and a direction control input (DIR). When DIR is high, data flows from
the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The HD74HCT245
transfers true data from one bus to the other.
This device does not have schmitt trigger inputs.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (A to Y) = 12 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC245P
DILP-20 pin
PRDP0020AC-B P
—
(DP-20NEV)
HD74HC245FPEL SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
EL (2,000 pcs/reel)
PRSP0020DC-A
HD74HC245RPEL SOP-20 pin (JEDEC) (FP-20DBV)
RP
EL (1,000 pcs/reel)
HD74HC245TELL TSSOP-20 pin
PTSP0020JB-A
T
(TTP-20DAV)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Enable G
L
L
H
H : high level
L : low level
X : irrelevant
Direction Control DIR
L
H
X
Operation
B data to A bus
A data to B bus
Isolation
Rev.2.00 Mar 30, 2006 page 1 of 6
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