HD74HCT373P データシートの表示（PDF） - Renesas Electronics
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HD74HCT373P Datasheet PDF : 9 Pages
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HD74HCT373, HD74HCT533
Octal D-type Transparent Latches (with 3-state outputs)
Octal D-type Transparent Latches (with inverted 3-state outputs)
REJ03D0666–0200
(Previous ADE-205-555)
Rev.2.00
Mar 30, 2006
Description
When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of
HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input, all outputs go to a high impedance state, regardless of what signals present at the other inputs and the state of the
storage elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HCT373P
DILP-20 pin
PRDP0020AC-B
P
(DP-20NEV)
HD74HCT373FPEL SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
HD74HCT373RPEL
PRSP0020DC-A
HD74HCT533RPEL SOP-20 pin (JEDEC) (FP-20DBV)
RP
HD74HCT373TELL TSSOP-20 pin
PTSP0020JB-A
T
(TTP-20DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Output Control
Enable G
D
L
H
H
L
H
L
L
L
X
H
X
X
Notes: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
HD74HCT373
Q
H
L
No change
Z
HD74HCT533
Q
L
H
No change
Z
Rev.2.00 Mar 30, 2006 page 1 of 8
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