HD74LS165AFP データシートの表示（PDF） - Renesas Electronics

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HD74LS165AFP

Parallel-Load 8-bit Shift Register

Renesas Electronics 

HD74LS165A

Waveforms 2

Clock Inhibit

Input

Clock

Input

1.3V

tsu

3V

(Disable while

clock is high)

0V

3V

1.3V 1.3V 1.3V

tsu

tw (clock)

0V

3V

F and H

1.3V 1.3V

1.3V

1.3V

Inputs

(See Notes A and B)

tsu

tw (load)

0V

tw (load)

3V

Shift/

Load

1.3V 1.3V 1.3V 1.3V

0V

tPHL

Output QH

tPLH

1.3V

tPHL

1.3V

tPLH

1.3V

tPHL

1.3V

tPLH

1.3V

VOH

VOL

tPLH

Output QH

tPHL

1.3V 1.3V

tPLH

1.3V

tPHL

1.3V

tPLH

1.3V

tPHL

1.3V

VOH

VOL

Notes:

A. The remaining six data inputs and the serial input are low.

B. Prior to test, high-level data is loaded into H input.

C. The input pulse Generators have the following characteristics: PRR ≤ 1 MHz,

duty cycle ≤ 50%, Zout ≈ 50 Ω, tTLH ≤ 15 ns, tTHL ≤ 6 ns.

Rev.3.00, Jul.15.2005, page 5 of 7

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