HD74LS194AFPEL データシートの表示（PDF） - Renesas Electronics
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HD74LS194AFPEL Datasheet PDF : 8 Pages
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HD74LS194A
Function Table
Inputs
Outputs
Mode
Serial
Clear
Clock
S1
S0
Left Right A
Parallel
B
C
D
QA
QB
QC
QD
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
H
↑
X
X
a
b
c
d
a
b
c
d
H
L
H
↑
X
H
X
X
X
X
H
QAn
QBn
QCn
H
L
H
↑
X
L
X
X
X
X
L
QAn
QBn
QCn
H
H
L
↑
H
X
X
X
X
X
QBn
QCn
QDn
H
H
H
L
↑
L
X
X
X
X
X
QBn
QCn
QDn
L
H
L
L
X
X
X
X
X
X
X
QAo
QBo
QCo
QDo
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. a to d; the level of steady-state input at inputs A, B, C, or D, respectively
4. QA0 to QD0; the level of QA, QB, QC, or QD, respectively before the indicated steady-state input conditions were
established.
5. QAn to QDn; the level of QA, QB, QC, or QD, respectively before the most-recent ↑ transition of the clock.
Block Diagram
Parallel Inputs
A
B
C
D
Mode S1
Control
Inputs S0
Shift
Right
Serial
Input
Shift
Left
Serial
Input
Clock
Clear
S QA
CK
R
Clear
S QB
CK
R
Clear
S QC
CK
R
Clear
S QD
CK
R
Clear
QA
QB
QC
QD
Parallel Outputs
Rev.3.00, Jul.15.2005, page 2 of 7
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