HEF4046BP データシートの表示（PDF） - Philips Electronics

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HEF4046BP

Phase-locked loop

Philips Electronics 

Philips Semiconductors

Phase-locked loop

Product specification

HEF4046B

MSI

DESIGN INFORMATION

CHARACTERISTIC

No signal on SIGNIN

Phase angle between

SIGNIN and COMPIN

Locks on harmonics of

centre frequency

Signal input noise

rejection

Lock frequency

range (2 fL)

Capture frequency

range (2 fC)

Centre frequency (fo)

USING PHASE COMPARATOR 1

VCO in PLL system adjusts

to centre frequency (fo)

90° at centre frequency (fo),

approaching 0° and 180° at

ends of lock range (2 fL)

yes

USING PHASE COMPARATOR 2

VCO in PLL system adjusts to min.

frequency (fmin)

always 0° in lock

(positive-going edges)

no

high

low

the frequency range of the input signal on which the loop will stay locked if it was

initially in lock; 2 fL = full VCO frequency range = fmax − fmin

the frequency range of the input signal on which the loop will lock if it was initially

out of lock

depends on low-pass

filter characteristics; fC < fL

fC = fL

the frequency of the VCO when VCOIN at 1⁄2VDD

VCO component selection

Recommended range for R1 and R2: 10 kΩ to 1 MΩ; for C1: 50 pF to any practical value.

1. VCO without frequency offset (R2 = ∞).

a) Given fo: use fo with Fig.7 to determine R1 and C1.

b) Given fmax: calculate fo from fo = 1⁄2 fmax; use fo with Fig.7 to determine R1 and C1.

2. VCO with frequency offset.

a) Given fo and fL : calculate fmin from the equation fmin = fo − fL; use fmin with Fig.8 to determine R2 and C1; calculate

f-f-m-m----ai-n-x- from the equation -ff-m-m----ai-n-x- = f-f-o-o---+-–----ff--LL- ; use -ff-m-m----ai-n-x- with Fig. 9 to determine the ratio R2/R1 to obtain R1.

b) Given fmin and fmax: use fmin with Fig.8 to determine R2 and C1; calculate

f-f-m-m----ai--nx- ; use -ff-m-m----ai-n-x-

with Fig.9 to determine R2/R1 to obtain R1.

January 1995

9

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