HI-8010 データシートの表示（PDF） - Holt Integrated Circuits
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HI-8010 Datasheet PDF : 9 Pages
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HI-8010/HI-8110 Series
PIN DESCRIPTIONS
SYMBOL
VSS
CS
CL
LD
DIN
LCD0
LCD0OPT
VDD
VEE
DOUT
BP
Segments
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
OUTPUT
0 Volts
Logic input
Logic input
Logic input
Logic input
Analog input
Analog output
5 Volts
0 Volts to -30 Volts
Logic output
Display drive output
Display drive output
DESCRIPTION
Chip select
Clocks shift register on negative edge and DOUT pins on positive edge
Segment outputs equal shift register data if Load is high
Shift register data input
Display clock input and is always bonded out. Can swing from VEE to VDD
Bonded out only if an RC oscillator is required
Selected pinout can provide shift register taps at positions 30, 32, 34, or 38
Low resistance drive for the backplane and swings from VDD to VEE
High resistance drive for each segment and swings from VDD to VEE
FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (CS)
input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (CL) input. CS is internally tied to VSS on some
versions. A Logic "1" present at the Load (LD) input will
cause a parallel transfer of data from the shift register to the
data latch. If the Load (LD) input is held high while data is
clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8010 and
CMOS compatible on the HI-8110.
on the rising edge of the Clock (CL). Clock (CL), Load (LD)
and Chip Select (CS) should be tied in common with each
other, respectively, between all cascaded display drivers.
INTERNAL OSCILLATOR CIRCUIT
To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-of-
phase with the backplane.
The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150KW resistor with a 470pF capacitor generates an
approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency is divided by 256 to
determine the backplane output frequency. The resistor
value (R) must be at least 30KW for proper self-oscillator
operation.
LCDØ
LCDØ
OPT
For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc. (See Figures 2 & 3). Data out (DOUT) will change state
R
C
÷ 256
Q
TO BACKPLANE
TRANSLATOR
AND DRIVER
Figure 1
HOLT INTEGRATED CIRCUITS
2
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