HI7190EVAL_ データシートの表示（PDF） - Intersil
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HI7190EVAL_ Datasheet PDF : 25 Pages
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HI7191
transfer formats including both the Motorola 6805/11 series
SPI and Intel 8051 series SSR protocols. Data Integrity is
always maintained at the HI7191 output port. This means
that if a data read of conversion N is begun but not finished
before the next conversion (conversion N + 1) is complete,
the DRDY line remains active (low) and the data being read
is not overwritten.
The HI7191 provides many calibration modes that can be
initiated at any time by writing to the Control Register. The
device can perform system calibration where external
components are included with the HI7191 in the calibration
loop or self-calibration where only the HI7191 itself is in the
calibration loop. The On-chip Calibration Registers are
read/write registers which allow the user to read calibration
coefficients as well as write previously determined
calibration coefficients.
Circuit Operation
The analog and digital supplies and grounds are separate
on the HI7191 to minimize digital noise coupling into the
analog circuitry. Nominal supply voltages are AVDD = +5V,
DVDD = +5V, and AVSS = -5V. If the same supply is used
for AVDD and DVDD it is imperative that the supply is
separately decoupled to the AVDD and DVDD pins on the
HI7191. Separate analog and digital ground planes should
be maintained on the system board and the grounds should
be tied together back at the power supply.
When the HI7191 is powered up it needs to be reset by
pulling the RESET line low. The reset sets the internal
registers of the HI7191 as shown in Table 2 and puts the part
in the bipolar mode with a gain of 1 and offset binary coding.
The filter notch of the digital filter is set at 30Hz while the I/O
is set up for bidirectional I/O (data is read and written on the
SDIO line and SDO is three-stated), descending byte order,
and MSB first data format. A self calibration is performed
before the device begins converting. DRDY goes low when
valid data is available at the output.
TABLE 2. REGISTER RESET VALUES
REGISTER
VALUE (HEX)
Data Output Register
XXXX (Undefined)
Control Register
28B300
Offset Calibration Register
Self Calibration Value
Positive Full Scale Calibration Self Calibration Value
Register
Negative Full Scale Calibration Self Calibration Value
Register
The configuration of the HI7191 is changed by writing new
setup data to the Control Register. Whenever data is written
to byte 2 and/or byte 1 of the Control Register the part
assumes that a critical setup parameter is being changed
which means that DRDY goes high and the device is re-
synchronized. If the configuration is changed such that the
device is in any one of the calibration modes, a new
calibration is performed before normal conversions continue.
If the device is written to the conversion mode, a new
calibration is NOT performed (A new calibration is
recommended any time data is written to the Control
Register). In either case, DRDY goes low when valid data is
available at the output.
If a single data byte is written to byte 0 of the Control
Register, the device assumes the gain has NOT been
changed. It is up to the user to re-calibrate the device if the
gain is changed in this manner. For this reason it is
recommended that the entire Control Register be written
when changing the gain of the device. This ensures that the
part is re-calibrated (if in a calibration mode) before the
DRDY output goes low indicating that valid data is available.
The calibration registers can be read via the serial interface
at any time. However, care must be taken when writing data
to the calibration registers. If the HI7191 is internally
updating any calibration register the user can not write to
that calibration register. See the Operational Modes section
for details on which calibration registers are updated for the
various modes.
Since access to the calibration registers is asynchronous to
the conversion process the user is cautioned that new
calibration data may not be used on the very next set of
“valid” data after a calibration register write. It is guaranteed
that the new data will take effect on the second set of output
data. Non-calibrated data can be obtained from the device
by writing 000000 (h) to the Offset Calibration Register,
800000 (h) to the Positive Full Scale Calibration Register,
and 800000 (h) to the Negative Full Scale Calibration
Register. This sets the offset correction factor to 0 and the
positive and negative gain slope factors to 1.
If several HI7191s share a system master clock the SYNC
pin can be used to synchronize their operation. A common
SYNC input to multiple devices will synchronize operation
such that all output registers are updated simultaneously. Of
course the SYNC pin would normally be activated only after
each HI7191 has been calibrated or has had calibration
coefficients written to it.
The SYNC pin can also be used to control the HI7191 when
an external multiplexer is used with a single HI7191. The
SYNC pin in this application can be used to guarantee a
maximum settling time of 3 conversion periods when
switching channels on the multiplexer.
Analog Section Description
Figure 6 shows a simplified block diagram of the analog
modulator front end of a sigma delta A/D Converter. The
input signal VIN comes into a summing junction (the PGIA in
this case) where the previous modulator output is subtracted
from it. The resulting signal is then integrated and the output
10
FN4138.8
June 1, 2006
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