HIP5062 データシートの表示（PDF） - Intersil

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HIP5062

Power Control IC Single Chip Dual Switching Power Supply

Intersil 

HIP5062

Pin Descriptions

PAD NUMBER

1, 4, 7

2, 3, 5, 6

8

9

10

11

12

13

14

15

16

17

18

19

20

22, 23, 25, 26

21, 24, 27

28

29

30

31

DESIGNATION

DESCRIPTION

S2

Source pads for the channel 2 regulator.

D2

Drain pads for the channel 2 regulator.

VDDP2

This pad is the power input for the channel 2 DMOS gate driver and also is used to decouple the

high current pulses to the output driver transistors. The decoupling capacitor should be at least

a 0.1µF chip capacitor placed close to this pad and the DMOS source pads.

VCMP2

Output of the second channel transconductance amplifier. This node is used for both gain and

frequency compensation of the loop.

PSOK

This pad provides delayed positive indication when both supplies are enabled.

VREG2

Input to the transconductance error amplifier. The other common input for both amplifiers is

VINP, Pad 36.

FLTN

This is an open drain output that remains low when V+ is too low for proper operation. This node

and PSEN are useful in multiple converter configurations. This pad will be latched low when over-

temperature, over-voltage or over-current is experienced. V+ must be powered down to reset.

PSEN

This terminal is provided to activate the converter. When the input is low, the DMOS drivers are

disabled. There is an internal 12K pull-up resistor on this terminal.

SHRT

50µA is internally applied to this node when there is an over-current condition.

SLRN

Control input to internal regulator that is used during the “start-up” of the supply. In normal oper-

ation this terminal starts at 0V and shuts down the internal regulator at approximately 9V. This

pad is usually connected to SFST, pad 16.

SFST

Controls the rate of rise of both output voltages. Time is determined by an internal 1µA current

source and an external capacitor.

VDDD

VDDA

Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply.

This is the analog supply and internal 12V regulator output usually used only during the start-up

sequence. The internal regulator reduced to a nominal 9.2V when SLRN is returned to 12V. Out-

put current capability is 30mA at both voltages.

VREG1

Input to channel one transconductance error amplifier. The other, common input for both ampli-

fiers is VINP, pad 36.

VDDP1

This pad is the power input for the channel 1 DMOS gate driver and also is used to decouple the

high current pulses to the output driver transistors. The decoupling capacitor should be at least

a 0.1µF chip capacitor placed close to this pad and the DMOS source pads.

D1

Drain pads for the channel 1 regulator.

S1

Source pads for the channel 1 regulator.

VTCN

Input to transconductance amplifier buffer for channel 1 only. Normally connected to VCMP1,

pad 29.

VCMP1

Output of the first channel transconductance amplifier. This node is used for both gain and fre-

quency compensation of the loop.

IRFO1

A resistor placed between this pad and IRFI1 converts the VCMP1 signal to a current for the cur-

rent sense comparator. The maximum current is set by the value of the resistor, according to the

equation: IPEAK = 16/R. Where R is the value of the external resistor in KΩ and must be greater

than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will

be 8.8A. This assumes VCMP1 is 7.3V. Maximum output current should be kept below 10A.

IRFI1

See IRFO1.

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