HM-65642 データシートの表示（PDF） - Intersil
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HM-65642 Datasheet PDF : 7 Pages
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HM-65642
AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-65642-9)
SYMBOL
PARAMETER
LIMITS
MIN
MAX
UNITS
TEST
CONDITIONS
READ CYCLE
(1) TAVAX
Read Cycle Time
150
-
ns
(Notes 1, 3)
(2) TAVQV
Address Access Time
-
150
ns
(Notes 1, 3)
(3) TE1LQV
Chip Enable Access Time
E1
-
150
ns
(Notes 2, 3)
(4) TE2HQV
Chip Enable Access Time
E2
-
150
ns
(Notes 1, 3)
(5) TGLQV
Output Enable Access Time
-
70
ns
(Notes 1, 3)
(6) TE1LQX
Chip Enable Valid to Output On
E1
10
-
ns
(Notes 2, 3)
(7) TE2HQX
Chip Enable Valid to Output On
E2
10
-
ns
(Notes 2, 3)
(8) TGLQX
Output Enable Valid to Output On
5
-
ns
(Notes 2, 3)
(9) TE1HQZ
Chip Enable Not Valid to Output Off
E1
-
50
ns
(Notes 2, 3)
(10) TE2LQZ
Chip Enable Not Valid to Output Off
E2
-
60
ns
(Notes 2, 3)
(11) TGHQZ
Output Enable Not Valid to Output Off
-
50
ns
(Notes 2, 3)
(12) TAXQX
Output Hold From Address Change
10
-
ns
(Notes 2, 3)
WRITE CYCLE
(13) TAVAX
Write Cycle Time
150
-
ns
(Notes 1, 3)
(14) TWLWH
Write Pulse Width
90
-
ns
(Notes 1, 3)
(15) TE1LE1H Chip Enable to End of Write
E1
90
-
ns
(Notes 1, 3)
(16) TE2HE2L Chip Enable to End of Write
E2
90
-
ns
(Notes 1, 3)
(17) TAVWL
Address Setup Time
Late Write
0
-
ns
(Notes 1, 3)
(18) TAVE1L
Address Setup Time
Early Write
E1
0
-
ns
(Notes 1, 3)
(19) TAVE2H
Address Setup Time
Early Write
E2
0
-
ns
(Notes 1, 3)
(20) TWHAX
Write Recovery Time
Late Write
10
-
ns
(Notes 1, 3)
(21) TE1HAX
Write Recovery Time
Early Write
E1
10
-
ns
(Notes 1, 3)
(22) TE2LAX
Write Recovery Time
Early Write
E2
10
-
ns
(Notes 1, 3)
(23) TDVWH
Data Setup Time
Late Write
60
-
ns
(Notes 1, 3)
(24) TDVE1H
Data Setup Time
Early Write
E1
60
-
-
(Notes 1, 3)
(25) TDVE2L
Data Setup Time
Early Write
E2
60
-
ns
(Notes 1, 3)
(26) TWHDX
Data Hold Time
Late Write
5
-
ns
(Notes 1, 3)
(27) TE1HDX
Data Hold Time
Early Write
E1
10
-
ns
(Notes 1, 3)
(28) TE2LDX
Data Hold Time
Early Write
E2
10
-
ns
(Notes 1, 3)
(29) TWLQZ
Write Enable Low to Output Off
-
50
ns
(Notes 2, 3)
(30) TWHQX
Write Enable High to Output On
5
-
ns
(Notes 2, 3)
NOTES:
1. Input pulse levels: 0V to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
6-4
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