HM5259165B-75 データシートの表示（PDF） - Elpida Memory, Inc

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HM5259165B-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5259165B/HM5259805B/HM5259405B-75/A6

Block Diagram (HM5259165B)

Column address

counter

A0 to A12, BA0, BA1

Upper pellet

A0 to A9

Column address

buffer

A0 to A12, BA0, BA1

Row address

buffer

Refresh

counter

Row decoder

Memory array

Bank0

8192 row

× 1024 column

× 8 bit

Row decoder

Memory array

Bank1

8192 row

× 1024 column

× 8 bit

Row decoder

Memory array

Bank2

8192 row

× 1024 column

× 8 bit

Row decoder

Memory array

Bank3

8192 row

× 1024 column

× 8 bit

Input buffer Output buffer

DQ8 to DQ15

DQ0 to DQ7

Input buffer Output buffer

CLK

CKE

CS

RAS

CAS

WE

DQMU

/DQML

Memory array

Bank0

8192 row

× 1024 column

× 8 bit

Row decoder

Column address

counter

Memory array

Bank1

8192 row

× 1024 column

× 8 bit

Row decoder

Memory array

Bank2

8192 row

× 1024 column

× 8 bit

Row decoder

Column address

buffer

Row address

buffer

Memory array

Bank3

8192 row

× 1024 column

× 8 bit

Row decoder

Refresh

counter

Lower pellet

Data Sheet E0118H10

6

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