NVM3060 データシートの表示（PDF） - Micronas
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NVM3060 Datasheet PDF : 13 Pages
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NVM 3060
5. Description of the IM Bus
The INTERMETALL Bus (IM Bus for short) has been de-
signed to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means the CCU acts
as a master whereas all controlled ICs are slaves.
The IM Bus consists of three lines for the signals Ident
(ID), Clock (CL) and Data (D). The clock frequency
range is 50 Hz to 170 kHz. Ident and clock are unidirec-
tional from the CCU to the slave ICs, Data is bidirec-
tional. Bidirectionality is achieved by using open-drain
outputs with On-resistances of 150 Ω maximum. The
2.5 kΩ pull-up resistor common to all outputs is incorpo-
rated in the CCU.
The timing of a complete IM Bus transaction is shown in
Fig. 5–1. In The non-operative state the signals of all
three bus lines are High. To start a transaction the CCU
sets the ID signal to Low level, indicating an address
transmission, and sets the CL signal to Low level as well
to switch the first bit on the Data line. Thereafter eight
address bits are transmitted beginning with the LSB.
Data takeover in the slave ICs occurs at the positive
edge of the clock signal. At the end of the address byte
the ID signal goes High, initiating the address compari-
son in the slave circuits. In the addressed slave the IM
bus interface switches over to Data read or write, be-
cause these functions are correlated to the address.
Also controlled by the address the CCU now transmits
eight or sixteen clock pulses, and accordingly one or two
bytes of data are written into the addressed IC or read
out from it, beginning with the LSB.
The completion of the bus transaction is signalled by a
short Low-state pulse of the ID signal. This initiates the
storing of the transferred data.
It is permissible to interrupt a bus transaction for up to
10 ms.
H
Ident
L
H
Clock
L
H
Data
L
1 2 3 4 5 6 7 8 9 10 11 12 13
LSB
Address
MSB LSB
Data
A
Section A
B
Section B
H
Ident
L
tIM
1
H
Clock
L
H
Data
L
tIM
tIM
3
2
tIM
tIM
tIM
7
8
9
Address LSB
tIM tIM
4
5
Address MSB
24
MSB
C
Section C
tIM1
0
tIM
6
Data MSB
Fig. 5–1: IM bus waveforms
10
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