HS3160 データシートの表示（PDF） - Signal Processing Technologies

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HS3160

16-Bit Multiplying DACs

Signal Processing Technologies 

2 - 1(MSB)

2 -2

0

0

0

1

1

0

1

1

Output

0

1/4 Full-Scale

1/2 Full-Scale

3/4 Full-Scale

Table 1. Contribution of the two MSB's

The most common technique for building a D/A

converter of n bits is to use n switches to turn n current

or voltage sources on or off. The n switches and n

sources are designed so that each switch or bit contrib-

utes twice as much to the D/A converter’s output as the

preceding bit. This technique is commonly known as

binary weighting and allows an n-bit converter to

generate 2n output levels by turning on the proper

combination of bits.

In such a binary-weighted converter, the switch

with the smallest contribution (the LSB) accounts

for only 2 -n of the converter’s full-scale value.

Similarly, the switch with the largest contribution

(the MSB) accounts for 2 -1 or half of the converter’s

full-scale output. Thus it is easy to see that a given

percent change in the MSB will have a greater

effect on the converter’s output than would a

similar percent change in the LSB. For example, a

1% change in the LSB of a 10 bit converter would

only affect the output by 0.001% of full-scale. A

1% change in the MSB of the same converter

would affect the output by 0.5% of FSR.

In order to overcome the problem which results from

the large weighting of the MSB, the two MSB’s can

be decoded to three equally weighted sources. Table

1 shows that all combinations of the two MSB’s of a

converter result in four output levels. So by replacing

the two MSB’s with three bits equally weighted at 1/

4 full-scale and decoding the two MSB digital inputs

into three lines which drive the equally weighted bits,

TRANSFER FUNCTION (N=16)

BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT

111...111

100...001

100...000

011...111

000…001

000...000

–VREF (1 - 2–N)

–VREF (1/2 + 2–N)

–VREF /2

–VREF (1/2 – 2–N)

–VREF (2(N – 1))

0

–VREF (1 – 2 –(N – 1))

–VREF (2 ) –(N – 1)

0

VREF (2 ) –(N – 1)

VREF (1 – 2 –(N – 1))

VREF

Table 2. Transfer Function

400Ω

V REF

470Ω

V DD

DIGITAL

INPUTS

SP7516

HS3160

RFEEDBACK

I O1

I O2

200Ω

ROS

-

A

+

V OUT

GND

Figure 2. Unipolar Operation

the same functional performance can be obtained.

Thus by replacing the two MSB switches of a conven-

tional converter with three switches properly de-

coded, the contribution of any switch is reduced from

1/2 to 1/4. This reduction in sensitivity also reduces the

accuracy required of any switch for a given overall

converter accuracy.

With the decoded converter described above, a 1%

change in any of the converter’s switches will affect

the output by no more than 0.25% of full-scale as

compared to 0.5% for a conventional converter. In

other words the conventional D/A converter can be

made less sensitive to the quality of its individual bits

by decoding.

In the SP7516/HS3160 the first four MSB’s are

decoded into 16 levels which drive 15 equally weighted

current sources. The sensitivity of each switch on the

output is reduced by a factor of 8. Each of the 15

sources contributes 6.25% output change rather than

an MSB change of 50% for the common approach.

400Ω

V REF

470Ω

V DD

200Ω

RFEEDBACK

I O1

DIGITAL

INPUTS

SP7516

HS3160

4KΩ

4KΩ

IO2

GND

ROS2 R

ROS2

-

A2

+

ROS1

-

A1

+

VOUT

V OUT1

A1, A2 , OP-07

Figure 3. Bipolar Operation

Corporation

SIGNAL PROCESSING EXCELLENCE

131

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