HSD4M64B4W データシートの表示（PDF） - Hanbit Electronics Co.,Ltd

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HSD4M64B4W

Synchronous DRAM Module 32Mbyte(4Mx64-Bit), 144pin SO-DIMM, 4Banks, 4K Ref., 3.3V

Hanbit Electronics Co.,Ltd 

HANBit

HSD4M64B4W

CKE ≥ VIH(min)

ICC2NS

CLK ≤ VIL(max), tCC=∞

24

Input signals are stable

ICC3P

Active standby current in

power-down mode

ICC3PS

CKE ≤ VIL(max), tCC=10ns

CKE&CLK ≤ VIL(max)

tCC=∞

12

mA

12

CKE≥VIH(min),

CS*≥VIH(min), tCC=10ns

ICC3N

100

Active standby current in

Input signals are changed

non power-down mode

one time during 20ns

mA

(One bank active)

CKE≥VIH(min)

ICC3NS

CLK ≤VIL(max), tCC=∞

60

Input signals are stable

Operating current

(Burst mode)

IO = 0 mA

Page burst

ICC4

4Banks Activated

540 520 440 440 mA

1

tCCD = 2CLKs

Refresh current

ICC5

tRC ≥ tRC(min)

540 520 440 440 mA

2

Self refresh current

ICC6

CKE ≤ 0.2V

4

mA

1.6

mA

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).

AC OPERATING TEST CONDITIONS

(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)

PARAMETER

AC Input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

UNIT

V

V

Ns

V

URLwww.hbe.co.kr

Rev.0.0 (March / 2002)

6

HANBit Electronics Co.,Ltd.

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