HSD4M64B4W データシートの表示（PDF） - Hanbit Electronics Co.,Ltd

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HSD4M64B4W

Synchronous DRAM Module 32Mbyte(4Mx64-Bit), 144pin SO-DIMM, 4Banks, 4K Ref., 3.3V

Hanbit Electronics Co.,Ltd 

HANBit

HSD4M64B4W

3.3V

DOUT

870Ω

1200Ω

50pF*

DOUT

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

(Fig. 1) DC output load

Vtt=1.4V

Z0=50Ω

50Ω

50pF

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

PARAMETER

SYMBOL

Row active to row active delay

RAS to CAS delay

Row precharge time

Row active time

tRRD(min)

tRP(min)

tRP(min)

tRAS(min)

tRAS(max)

Row cycle time

tRC(min)

Last data in to row precharge

tRDL(min)

Last data in to Active delay

tDAL(min)

Last data in to new col. address delay

tCDL(min)

Last data in to burst stop

tBDL(min)

Col. address to col. address delay

tCCD(min)

Number of valid output data

CAS latency=3

CAS latency=2

VERSION

-13

-12

-10

-10L

15

16

20

20

20

20

20

20

20

20

20

20

45

48

50

50

100

65

68

70

70

2

2 CLK + 20 ns

1

1

1

2

-

1

UNIT

ns

ns

ns

ns

ns

ns

CLK

CLK

CLK

CLK

ea

NOTE

1

1

1

1

1

2.5

2

2

3

4

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

.

URLwww.hbe.co.kr

Rev.0.0 (March / 2002)

7

HANBit Electronics Co.,Ltd.

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