HSP-EVAL データシートの表示（PDF） - Intersil

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HSP-EVAL

DSP Evaluation Platform

Intersil 

HSP-EVAL

PCWR0

PCWR1

PCD0-7

DATA

0x46 (HEX)

0x06 (HEX)

DATA FOR

LSBYTE OF

INPUT REG 1

WRITTEN TO

HOLDING REG

ADDRESS OF LD BIT OF

INPUT REG 1 ADDRESS REG

WRITTEN TO TOGGLED TO

ADDRESS LOAD DATA

REG

INTO LSBYTE

OF INPUT REG 1

FIGURE 2. TIMING DIAGRAM FOR A LOADING DATA INTO

LSBYTE OF INPUT REGISTER 1

Daughter Board Clocking Modes

The HSP-EVAL provides the daughter board with one of

three jumper selectable clock sources. The three clock

choices consist of an on-board oscillator, a user provided

external clock, and a clock generated by toggling the LSB of

the CTL Control Register. The clock source is select by

placing a jumper in the Clock Select Portion of the J4

Configuration Jumper Field. The selected clock source is

provided to the daughter board through the J1 Input

Connector. To support applications in which multiple HSP-

EVALs are daisy chained together, a clock output line is

routed from the Daughter Board Output Connector J2 to the

HSP-EVAL's 96 Pin Output Connector P2.

The on-board oscillator is selected as a clock source by

inserting a jumper at the OSC_CLK position in the J4 jumper

field. In this mode, the oscillator on-board the HSP-EVAL is

supplied as a clock to the daughter board. Since data

transfers to the daughter board via the HSP-EVAL’s I/O

registers are much slower than the daughter board’s data

rate using the oscillator clock, the HSP-EVAL is used to

provide the daughter board with asynchronous control in this

mode.

An external clock may be selected by inserting a jumper at

the EXT_CLK position in the J4 Jumper Field. In this mode,

an external clock supplied to the CLKIN Pin of the 96 Pin

Input Connector is provided to the daughter board. This

configuration supports the use of a common clock between

daisy-chained HSP-EVALs by wiring CLKOUT from the P2

Output Connector of one board to the CLKIN pin of another

board's P1 Input Connector. Since there is no

synchronization between the externally provided clock and

data transfers to the HSP-EVAL's I/O Registers, the HSP-

EVAL typically provides the daughter board with

asynchronous control in this mode.

The LSB of the CTL Control Register is selected as the clock

source if a jumper is inserted in the CTL0 position of the J4

Configuration Jumper field. In this mode, the clock signal is

generated by using register writes to toggle the CTL0 bit.

Since the clock may be controlled by software, input and

Control Register writes and the Output Shift Register reads

can be performed synchronously with the clock.

Consequently, the HSP-EVAL, in combination with a

daughter board can be used as a hardware modeler where

input and output data vectors are transferred via a PC's

parallel port.

Configuration Jumper Field

The HSP-EVAL is configured for operation by placing

jumpers in the Configuration Jumper Field (J4). As shown in

Figure 4, the jumper field has areas dedicated for clock

selection, register output enables, board address selection,

and daughter board output selection. The default jumper

placement is shown as an overlay on the jumper field

schematic in Figure 4. Each HSP-EVAL leaves the factory

jumpered with the default configuration.

CTL3

CTL2

PCRD2

0

1

2

29

30

31

OUT2_0

OUT2_1

OUT1_13

OUT1_14

OUT1_15

FIGURE 3. TIMING DIAGRAMS FOR SHIFT REGISTER I/O

7

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