HSP43891GC-30 データシートの表示（PDF） - Intersil
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HSP43891GC-30 Datasheet PDF : 18 Pages
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HSP43891
Detailed operation of the DF to perform a basic 8-tap, 9-bit
coefficient, 9-bit data, 30MHz FIR filter is best understood by
observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREG0, MREG1, and TREG (Figures 1 and 2).
Therefore, the delay from presentation of data and
coefficients at the DIN0-8 and CIN0-8 inputs to a sum
appearing at the SUM0-25 output is: k + Td, where k = filter
length and Td = 4, the internal pipeline delay of the DF. After
the pipeline has filled, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td. The output sums, YN, shown in the
timing diagram are derived from the sum-of-products
equation.
7
YN = Σ CK XN–K
K=0
CLK
RESET
ERASE
DIN0-8
DIENB
CIN0-8
CIENB
ADR0-2
SUM0-25
SHADD
SENBL
SENBH
DCM0-1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18
C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5
012345670
Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14
0
FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING
SAMPLE
DATA IN (XN)
30MHz
CLOCK
DQ
CQ
+5V
ADR1
ADR2 SHADD
SENBL
ADR0
9
DIN0-8
VCC
SENBH
26
SUM0-25
DIENB
+5V
ADR1
ADR2
SHADD SENBL
9
ADR0
VCC
SENBH
26
DIN0-8
SUM0-25
DIENB
CLK
Y0
4-BIT Y1
CTR Y2
Y3
RESET
SYSTEM
RESET
9x16 COEFF
RAM/ROM
A0
A1
D0-D8
A2
A3
CLK
HSP43891
DF0
9
CIN0-8
9
COUT0-8
DCM1 RESET
VSS
CIENB DCM0 ERASE COENB
CLK
HSP43891
DF1
CIN0-8
9 NC
COUT0-8
DCM1 RESET
VSS
CIENB DCM0 ERASE COENB
SUM
OUT
(YN)
FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC
10
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