HT48CA0-2 データシートの表示（PDF） - Holtek Semiconductor
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HT48CA0-2 Datasheet PDF : 32 Pages
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HT48RA0-2/HT48CA0-2
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
Some registers remain unchanged during reset condi-
tions. Most registers are reset to the ²initial condition²
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different ²chip resets².
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
Note: ²u² means unchanged.
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem powers up or when the system awakes from a HALT
state.
When a system power up occurs, an SST delay is added
during the reset period. But when the reset comes from
the RES pin, the SST delay is disabled. Any wake-up
from HALT will enable the SST delay.
The functional unit chip reset status is shown below.
PC
WDT Prescaler
Input/Output ports
SP
Carrier output
000H
Clear
Input mode
Points to the top of the stack
Low level
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tS S T
Reset Timing Chart
V DD
RES
Reset Circuit
H A LT
W DT W DT
T im e - o u t
R eset
RES
O SC1
SST
1 0 -s ta g e
R ip p le C o u n te r
P o w e r - o n D e te c tio n
Reset Configuration
R eset
The chip reset status of the registers is summarized in the following table:
Register
Reset
WDT Time-out
RES Reset
(Power On) (Normal Operation) (Normal Operation)
Program Counter
000H
000H
000H
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
PA
1111 1111
1111 1111
1111 1111
PB
0011 1111
0011 1111
0011 1111
PC
---- ---1
---- ---1
---- ---1
RES Reset
(HALT)
000H
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--01 uuuu
1111 1111
0011 1111
---- ---1
WDT Time-out
(HALT)*
000H
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--11 uuuu
uuuu uuuu
uuuu uuuu
---- ---u
Note: ²u² means unchanged
²x² means unknown
Rev. 1.50
8
July 23, 2004
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