HT48RA0-3 データシートの表示（PDF） - Holtek Semiconductor
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HT48RA0-3 Datasheet PDF : 34 Pages
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HT48RA0-3/HT48CA0-3
A.C. Characteristics
Ta=25°C
Symbol
Parameter
fSYS
System Clock
Test Conditions
VDD
Conditions
3V fSYS=4MHz(±3%) ,
Temp. = 0°C ~ +50°C
Min.
3880
tSST
System Start-up Timer Period
¾
Power-up, reset or wake-up
from HALT
¾
tLVR
Low Voltage Width to Reset
¾
¾
0.25
tPOR
Power-on Reset Low Pulse Width ¾
¾
1
Note: tSYS=1/fSYS
Typ.
4000
1024
1
¾
Max.
4120
¾
2
¾
Unit
kHz
tSYS
ms
ms
Functional Description
Execution Flow
The HT48RA0-3/HT48CA0-3 system clock is an RC
type clock which requires the connection of an external
resistor for its operation. It is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
Program Counter - PC
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program memory are
executed and its contents specify a maximum of 1024
addresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
In s tr u c tio n C y c le
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
Skip
Program Counter + 2
Loading PCL
*9
*8
@7 @6 @5 @4 @3 @2 @1 @0
Jump, call branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
S9~S0: Stack register bits
@7~@0: PCL bits
Rev.1.10
4
October 12, 2007
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