HT48R03 データシートの表示（PDF） - Holtek Semiconductor
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HT48R03 Datasheet PDF : 38 Pages
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HT48R01/HT48R02/HT48R03
H T48R 01
0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
01H
M P0
0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
03H
M P1
04H
05H
ACC
06H
PCL
07H
TB LP
08H
TB LH
09H
W D TS
0A H
STATU S
0B H
IN T C 0
0C H
0D H
TM R 0
0E H
TM R 0C
0FH
10H
11H
12H
PA
13H
PAC
14H
PAPU
15H
PAW K
16H
C TR L
17H
W CON
18H
19H
1A H
1B H
1C H
1D H
1E H
1FH
20H
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
5FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0A H
0B H
0C H
0D H
0E H
S p e c ia l P u r p o s e 0 F H
D a ta M e m o ry
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1A H
1B H
1C H
1D H
1E H
1FH
20H
:U nused,
re a d a s "0 0 "
7FH
H T48R 02
In d ir e c t A d d r e s s in g R e g is te r 0
M P0
In d ir e c t A d d r e s s in g R e g is te r 1
M P1
ACC
PCL
TB LP
TB LH
W D TS
STATU S
IN T C 0
TM R 0
TM R 0C
TM R 1
TM R 1C
PA
PAC
PAPU
PAW K
C TR L
W CON
G e n e ra l P u rp o s e
D a ta M e m o ry
(9 6 B y te s )
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0A H
0B H
0C H
0D H
0E H
S p e c ia l P u r p o s e 0 F H
D a ta M e m o ry
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1A H
1B H
1C H
1D H
1E H
1FH
20H
:U nused,
re a d a s "0 0 "
BFH
H T48R 03
In d ir e c t A d d r e s s in g R e g is te r 0
M P0
In d ir e c t A d d r e s s in g R e g is te r 1
M P1
ACC
PCL
TB LP
TB LH
W D TS
STATU S
IN T C 0
TM R 0
TM R 0C
TM R 1
TM R 1C
PA
PAC
PAPU
PAW K
C TR L
W CON
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
RAM Mapping
S p e c ia l P u r p o s e
D a ta M e m o ry
:U nused,
re a d a s "0 0 "
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition opera-
tions related to the status register may give different re-
sults from those intended. The TO flag can be affected
only by system power-up, a WDT time-out or executing
the ²CLR WDT² or ²HALT² instruction. The PDF flag
can be affected only by executing the ²HALT² or ²CLR
WDT² instruction or a system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Bit No.
0
1
2
3
4
5
6~7
Label
C
AC
Z
OV
PDF
TO
¾
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.00
9
December 20, 2006
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