HT46R14-28 データシートの表示（PDF） - Holtek Semiconductor

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HT46R14-28

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R14

time-out or executing the ²CLR WDT² or ²HALT² in-

struction. The PDF flag can be affected only by exe-

cuting the ²HALT² or ²CLR WDT² instruction or a

system power-up.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

Interrupt

The devices provides two external interrupts, two inter-

nal timer/event counter 0/1 interrupts, one comparator

interrupt, and A/D converter interrupt. The interrupt con-

trol register 0 (INTC0;0BH) and interrupt control register

1 (INTC1;1EH) both contain the interrupt control bits

that are used to set the enable/disable status and inter-

rupt request flags.

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may take place during this interval,

but only the interrupt request flag will be recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. Once the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the SP is decremented. If immediate service

is desired, the stack should be prevented from becom-

ing full.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the program counter onto the

stack followed by a branch to a subroutine at the speci-

fied location in the ROM. Only the contents of the pro-

gram counter is pushed onto the stack. If the contents of

the register or of the status register (STATUS) is altered

by the interrupt service program which corrupts the de-

sired control sequence, the contents should be saved in

advance.

External interrupts are triggered by a high to low transi-

tion of INT0 or INT1, and the related interrupt request

flag (EI0F;bit 4 of the INTC0, EI1F;bit 5 of the INTC0) is

set as well. After the interrupt is enabled, the stack is not

full, and the external interrupt is active, a subroutine call

to location 04H or 08H occurs. The interrupt request flag

(EI0F or EI1F) and EMI bits are all cleared to disable

other interrupts.

The Comparator 0 output Interrupt is initialized by set-

ting the Comparator 0 output Interrupt request flag

(C0F; bit 6 of the INTC0), which is caused by a falling

edge transition of comparator 0 output. After the inter-

rupt is enabled, and the stack is not full, and the C0F bit

is set, a subroutine call to location 0CH occurs. The re-

lated interrupt request flag (C0F) is reset, and the EMI

bit is cleared to disable further maskable interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F;bit 4 of the INTC1), which is normally

caused by a timer overflow. After the interrupt is en-

abled, and the stack is not full, and the T0F bit is set, a

subroutine call to location 010H occurs. The related in-

terrupt request flag (T0F) is reset, and the EMI bit is

cleared to disable further interrupts. The Timer/Event

Counter 1 is operated in the same manner, The

Timer/Event Counter 1 related interrupt request flag is

T1F (bit 5 of the INTC1) and its subroutine call location

is 014H. The related interrupt request flag (T1F) will be

reset and the EMI bit cleared to disable further inter-

rupts.

Bit No. Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not take

0

C place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate

through carry instruction.

1

AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction, otherwise AC is cleared.

2

Z Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.

3

OV

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-

est-order bit, or vice versa, otherwise OV is cleared.

4

PDF PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by exe-

cuting the ²HALT² instruction.

5

TO

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

6, 7

¾ Unused bit, read as ²0²

Status (0AH) Register

Rev. 1.00

9

November 1, 2005

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