HT46R54 データシートの表示（PDF） - Holtek Semiconductor
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HT46R54 Datasheet PDF : 42 Pages
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HT46R53/HT46R54
A/D Converter
The 8 channels 12-bit resolution A/D converter are im-
plemented in this microcontroller.
The A/D converter contains 4 special registers which
are; ADRL (20H), ADRH (21H), ADCR (22H) and ACSR
(23H). The ADRH and ADRL are A/D result register
higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control regis-
ter, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the con-
verted analog channel, and give START bit a raising
edge and falling edge (0®1®0). At the end of A/D con-
version, the EOCB bit is cleared and an A/D converter
interrupt occurs (if the A/D converter interrupt is en-
abled). The ACSR is A/D clock setting register, which is
used to select the A/D clock source.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the are used to select an
analog input channel. There are a total of eight channels
to select. The bit5~bit3 of the ADCR are used to set PB
configurations. PB can be an analog input or as digital
I/O line determined by these 3 bits. Once a PB line is se-
lected as an analog input, the I/O functions and pull-high
resistor of this I/O line are disabled and the A/D con-
verter circuit is powered on. The EOCB bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when the A/D conversion is completed.
The START bit of the ADCR is used to begin the conver-
sion of the A/D converter. Giving START bit a rising edge
and falling edge means that the A/D conversion has
started. In order to ensure that the A/D conversion is
completed, the START should remain at ²0² until the
EOCB is cleared to ²0² (end of A/D conversion). Bit 7 of
the ACSR register is used for test purposes only and
must not be used for other purposes by the application
program. Bit1 and bit0 of the ACSR register are used to
select the A/D clock source.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialisation:
Special care must be taken to initialise the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialisation is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialis-
ation is not required.
Bit No. Label
Function
Selects the A/D converter clock source
0
1
ADCS0
ADCS1
00=
01=
10=
system
system
system
clock/2
clock/8
clock/32
11= undefined
2~6 ¾ Unused bit, read as ²0²
7 TEST For test mode used only
ACSR (23H) Register
Bit No. Label
Function
0 ACS0
1 ACS1 Defines the analog channel select
2 ACS2
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration se-
lect. If PCR0, PCR1 and PCR2 are all
zero, the ADC circuit is powered off to
reduce power consumption
Indicates end of A/D conversion.
(0= end of A/D conversion)
Each time bits 3~5 change state the
A/D should be initialised by issuing a
6 EOCB START signal, otherwise the EOCB
flag may have an undefined condition.
See ²Important note for A/D initialis-
ation².
Starts the A/D conversion.
7
START
0®1®0= Start
0®1= Reset A/D
converter
and
set
EOCB to ²1².
ADCR (22H) Register
ACS2 ACS1 ACS0 Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Analog Input Channel Selection
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL
(20H)
D3 D2 D1 D0
0
0
0
0
ADRH
(21H)
D11 D10 D9
D8
D7
D6
D5
D4
Note: D0~D11 is A/D conversion result data bit
LSB~MSB.
Rev. 1.40
18
July 12, 2005
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