HT46R54 データシートの表示（PDF） - Holtek Semiconductor
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HT46R54 Datasheet PDF : 42 Pages
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HT46R53/HT46R54
PCR2 PCR1 PCR0
7
6
5
4
3
0
0
0
PB7
PB6
PB5
PB4
PB3
0
0
1
PB7
PB6
PB5
PB4
PB3
0
1
0
PB7
PB6
PB5
PB4
PB3
0
1
1
PB7
PB6
PB5
PB4
PB3
1
0
0
PB7
PB6
PB5
PB4
AN3
1
0
1
PB7
PB6
PB5
AN4
AN3
1
1
0
PB7
PB6
AN5
AN4
AN3
1
1
1
AN7
AN6
AN5
AN4
AN3
Port B Configuration
STAR T
M in im u m o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d
2
PB2
PB2
PB2
AN2
AN2
AN2
AN2
AN2
1
PB1
PB1
AN1
AN1
AN1
AN1
AN1
AN1
0
PB0
AN0
AN0
AN0
AN0
AN0
AN0
AN0
EO CB
A /D s a m p lin g tim e
tA D C S
A /D s a m p lin g tim e
tA D C S
A /D s a m p lin g tim e
tA D C S
P C R 2~
PCR0
000B
A C S 2~
ACS0
000B
P o w e r-o n
R eset
100B
010B
S ta rt o f A /D
c o n v e r s io n
100B
000B
S ta rt o f A /D
c o n v e r s io n
101B
001B
S ta rt o f A /D
c o n v e r s io n
000B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
d o n 't c a r e
R e s e t A /D
c o n v e rte r
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
E n d o f A /D
c o n v e r s io n
tA D C
A /D c o n v e r s io n tim e
tA D C
A /D c o n v e r s io n tim e
tA D C
A /D c o n v e r s io n tim e
N o te : A /D c lo c k m u s t b e fS Y S /2 , fS Y S /8 o r fS Y S /3 2
tA D C S = 3 2 tA D
tA D C = 8 0 tA D
A/D Conversion Timing
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr EADI
; disable ADC interrupt
mov a,00000001B
mov ACSR,a
mov a,00100000B
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START
; reset A/D
clr START
; start A/D
Polling_EOC:
sz EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp polling_EOC
; continue polling
mov a,ADRH
; read conversion result high byte value from the ADRH register
mov adrh_buffer,a
; save result to user defined memory
mov a,ADRL
; read conversion result low byte value from the ADRL register
mov adrl_buffer,a
; save result to user defined memory
:
:
jmp start_conversion
; start next A/D conversion
Rev. 1.40
19
July 12, 2005
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